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PDF MAX1067 Data sheet ( Hoja de datos )

Número de pieza MAX1067
Descripción (MAX1067 / MAX1068) 200ksps Analog-to-Digital Converters
Fabricantes Maxim Integrated Products 
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No Preview Available ! MAX1067 Hoja de datos, Descripción, Manual

19-2955; Rev 1; 8/07
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
General Description
The MAX1067/MAX1068 low-power, multichannel, 14-
bit analog-to-digital converters (ADCs) feature a suc-
cessive-approximation ADC, integrated +4.096V
reference, a reference buffer, an internal oscillator,
automatic power-down, and a high-speed SPI™/
QSPI™/MICROWIRE™-compatible interface. The
MAX1067/MAX1068 operate with a single +5V analog
supply and feature a separate digital supply, allowing
direct interfacing with +2.7V to +5.5V digital logic.
The MAX1067/MAX1068 consume only 3.6mA (AVDD =
DVDD = +5V) at 200ksps when using an external refer-
ence. AutoShutdown™ reduces the supply current to
185µA at 10ksps and to less than 10µA at reduced sam-
pling rates.
The MAX1067 includes a 4-channel input multiplexer, and
the MAX1068 accepts up to eight analog inputs.
In addition, digital signal processor (DSP)-initiated con-
versions are simplified with the DSP frame-sync input and
output featured in the MAX1068. The MAX1068 includes a
data-bit transfer input to select between 8-bit-wide or 16-
bit-wide data-transfer modes. Both devices feature a scan
mode that converts each channel sequentially or one
channel continuously.
Excellent dynamic performance and low power, com-
bined with ease of use and an integrated reference,
make the MAX1067/MAX1068 ideal for control and data-
acquisition operations or for other applications with
demanding power consumption and space require-
ments. The MAX1067 is available in a 16-pin QSOP
package, and the MAX1068 is available in a 24-pin
www.DQatSaOShPeept4aUc.kcoamge. Both devices are guaranteed over the
commercial (0°C to +70°C) and extended (-40°C to
+85°C) temperature ranges. Use the MAX1168 evalua-
tion kit to evaluate the MAX1068.
Applications
Motor Control
Industrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Thermocouple Measurements
Accelerometer Measurements
Features
14-Bit Resolution, ±0.5 LSB INL and
±1 LSB DNL (max)
+5V Single-Supply Operation
Adjustable Logic Level (+2.7V to +5.25V)
Input Voltage Range: 0 to VREF
Internal (+4.096V) or External (+3.8V to AVDD)
Reference
Internal Track/Hold, 4MHz Input Bandwidth
Internal or External Clock
SPI/QSPI/MICROWIRE-Compatible Serial
Interface, MAX1068 Performs DSP-Initiated
Conversions
8-Bit-Wide or 16-Bit-Wide Data-Transfer Mode
(MAX1068 Only)
4-Channel (MAX1067) or 8-Channel (MAX1068)
Input Mux
Scan Mode Sequentially Converts Multiple
Channels or One Channel Continuously
Low Power
3.6mA at 200ksps
1.85mA at 100ksps
185µA at 10ksps
0.6µA in Full Power-Down Mode
Small Package Size
16-Pin QSOP (MAX1067)
24-Pin QSOP (MAX1068)
PART
MAX1067ACEE
MAX1067BCEE
MAX1067CCEE
MAX1067AEEE
MAX1067BEEE
MAX1067CEEE
Ordering Information
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
16 QSOP
16 QSOP
16 QSOP
16 QSOP
16 QSOP
16 QSOP
INL
(LSB)
±0.5
±1
±2
±0.5
±1
±2
Ordering Information continued at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX1067 pdf
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Shutdown Supply Current
IAVDD + CS = DVDD, SCLK = 0, DIN = 0,
IDVDD DSPR = DVDD, full power-down
0.6 10
µA
Power-Supply Rejection Ratio
PSRR AVDD = DVDD = 4.75V to 5.25V, full-scale
63
dB
input (Note 10)
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Acquisition Time
tACQ External clock (Note 6)
729
ns
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
tDO
tDV
tTR
tCSW
CDOUT = 30pF
CDOUT = 30pF
CDOUT = 30pF
50 ns
80 ns
80 ns
100 ns
CS to SCLK Setup
tCSS
SCLK rise
SCLK fall (DSP)
100 ns
CS to SCLK Hold
tCSH
SCLK rise
SCLK fall (DSP)
0 ns
SCLK High Pulse Width
tCH Duty cycle 45% to 55%
Conversion
Data transfer
93
50
ns
www.DaStaCSLhKeeLto4wU.Pcoumlse Width
Conversion
93
tCL Duty cycle 45% to 55%
Data transfer
50
ns
SCLK Period
tCP
209 ns
DIN to SCLK Setup
SCLK rise
tDS SCLK fall (DSP)
50 ns
DIN to SCLK Hold
SCLK rise
tDH SCLK fall (DSP)
0 ns
CS Falling to DSPR Rising
DSPR to SCLK Falling Setup
tDF
tFSS
100 ns
100 ns
DSPR to SCLK Falling Hold
tFSH
0 ns
_______________________________________________________________________________________ 5

5 Page





MAX1067 arduino
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
PIN
MAX1067 MAX1068
— 13
— 14
— 23
— 24
Pin Description (continued)
NAME
FUNCTION
AIN6
AIN7
DSPX
N.C.
Analog Input 6
Analog Input 7
DSP Frame-Sync Transmit Output. A frame-sync pulse at DSPX notifies the DSP that the
MSB data is available at DOUT. Leave DSPX unconnected when not in DSP mode.
No Connection. Not internally connected.
DVDD
DVDD
DOUT
1mA
DOUT
DOUT
1mA
DOUT
1mA CLOAD = 30pF
CLOAD = 30pF
1mA CLOAD = 30pF
CLOAD = 30pF
DGND
a) VOL TO VOH
DGND
b) HIGH-Z TO VOL AND VOH TO VOL
DGND
a) VOH TO HIGH-Z
DGND
b) VOL TO HIGH-Z
Figure 1. Load Circuits for DOUT Enable Time and SCLK-to-
DOUT Delay Time
Figure 2. Load Circuits for DOUT Disable Time
Detailed Description
The MAX1067/MAX1068 low-power, multichannel, 14-
bit ADCs feature a successive-approximation ADC,
automatic power-down, integrated +4.096V reference,
and a high-speed SPI/QSPI/MICROWIRE-compatible
www.DianttaeSrhfaeecte4U. .AcomDSPR input and DSPX output allow the
MAX1068 to communicate with DSPs with no external
glue logic. The MAX1067/MAX1068 operate with a sin-
gle +5V analog supply and feature a separate digital
supply allowing direct interfacing with +2.7V to +5.5V
digital logic.
Figures 3 and 4 show the functional diagrams of the
MAX1067/MAX1068, and Figures 5 and 6 show the
MAX1067/MAX1068 in a typical operating circuit. The
serial interface simplifies communication with micro-
processors (µPs).
In external reference mode, the MAX1067/MAX1068
have two power modes: normal mode and shutdown
mode. Driving CS high places the MAX1067/MAX1068
in shutdown mode, reducing the supply current to
0.6µA (typ). Pull CS low to place the MAX1067/
MAX1068 in normal operating mode. The internal refer-
ence mode offers software-programmable, power-down
options as shown in Table 5.
In SPI/QSPI/MICROWIRE mode, a falling edge on CS
wakes the analog circuitry and allows SCLK to clock in
data. Acquisition and conversion are initiated by SCLK.
The conversion result is available at DOUT in unipolar
serial format. DOUT is held low until data becomes
available (MSB first) on the 8th falling edge of SCLK
when in 8-bit transfer mode, and on the 16th falling
edge when in 16-bit transfer mode. See the Operating
Modes section. Figure 8 shows the detailed SPI/QSPI/
MICROWIRE serial-interface timing diagram.
In external clock mode, the MAX1068 also interfaces
with DSPs. In DSP mode, a frame-sync pulse from the
DSP initiates a conversion that is driven by SCLK. The
MAX1068 formats a frame-sync pulse to notify the DSP
that the conversion results are available at DOUT in
MSB-first, unipolar, serial-data format. Figure 16 shows
the detailed DSP serial-interface timing diagram (see the
Operating Modes section).
Analog Input
Figure 7 illustrates the input-sampling architecture of
the ADC. The voltage applied at REF or the internal
+4.096V reference sets the full-scale input voltage.
Track/Hold (T/H)
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive digital-to-analog converter
(DAC) samples the analog input.
______________________________________________________________________________________ 11

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