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PDF 28F640L18 Data sheet ( Hoja de datos )

Número de pieza 28F640L18
Descripción (28FxxxL18) StrataFlash Wireless Memory
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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Intel StrataFlash® Wireless Memory
(L18)
28F640L18, 28F128L18, 28F256L18
Datasheet
Product Features
High performance Read-While-Write/Erase
— 85 ns initial access
— 54 MHz with zero wait state, 14 ns clock-to-
data output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(BEFP) at 5 µs/byte (Typ)
— 1.8 V low-power buffered programming at
7 µs/byte (Typ)
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64-Mbit and 128-
Mbit devices
— Multiple 16-Mbit partitions: 256-Mbit devices
— Four 16-Kword parameter blocks: top or
bottom configurations
— 64-Kword main blocks
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Status Register for partition and device status
Power
— VCC (core) = 1.7 V - 2.0 V
— VCCQ (I/O) = 1.35 V - 2.0 V, 1.7 V - 2.0 V
— Standby current: 30 µA (Typ) for 256-Mbit
— 4-Word synchronous read current: 15 mA (Typ)
at 54 MHz
— Automatic Power Savings mode
Security
— OTP space:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OTP bits
— Absolute write protection: VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Intel® Flash Data Integrator optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
Quality and Reliability
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (0.13 µm)
Density and Packaging
— 64-, 128-, and 256-Mbit density in VF BGA
packages
— 128/0 and 256/0 density in SCSP
— 16-bit wide data bus
The Intel StrataFlash® wireless memory (L18) device is the latest generation of Intel
StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides
high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one
partition while code execution or data reads take place in another partition. This dual-operation
architecture also allows a system to interleave code operations while program and erase
operations take place in the background. The 8-Mbit or 16-Mbit partitions allow system
designers to choose the size of the code and data segments. The L18 wireless memory device is
manufactured using Intel 0.13 µm ETOX™ VIII process technology. It is available in industry-
standard chip scale packaging.
Order Number: 251902, Revision: 009
April 2005

1 page




28F640L18 pdf
Intel StrataFlash® Wireless Memory (L18)
14.0 Dual-Operation Considerations .......................................................................................71
14.1
14.2
14.3
Memory Partitioning ............................................................................................................71
Read-While-Write Command Sequences ...........................................................................71
14.2.1 Simultaneous Operation Details ............................................................................72
14.2.2 Synchronous and Asynchronous RWW Characteristics and Waveforms..............72
14.2.2.1 Write operation to asynchronous read transition ...................................72
14.2.2.2 Write to synchronous read operation transition .....................................73
14.2.2.3 Write Operation with Clock Active..........................................................73
14.2.3 Read Operation During Buffered Programming.....................................................73
Simultaneous Operation Restrictions .................................................................................74
15.0 Special Read States..............................................................................................................75
15.1 Read Status Register..........................................................................................................75
15.1.1 Clear Status Register.............................................................................................76
15.2 Read Device Identifier ........................................................................................................76
15.3 CFI Query ...........................................................................................................................77
Appendix A Write State Machine (WSM) ...........................................................................78
Appendix B Flowcharts ............................................................................................................85
Appendix C Common Flash Interface ................................................................................93
Appendix D Additional Information...................................................................................103
Appendix E Ordering Information......................................................................................104
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Datasheet
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
5

5 Page





28F640L18 arduino
Intel StrataFlash® Wireless Memory (L18)
2.0
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Functional Overview
The Intel StrataFlash® Wireless Memory (L18) provides read-while-write and read-while-erase
capability with density upgrades through 256-Mbit. This family of devices provides high
performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for
optimum code and data storage.
Each device density contains one parameter partition and several main partitions. The flash
memory array is grouped into multiple 8-Mbit or 16-Mbit partitions. By dividing the flash memory
into partitions, program or erase operations can take place at the same time as read operations.
Although each partition has write, erase, and burst read capabilities, simultaneous operation is
limited to write or erase in one partition while other partitions are in read mode. The Intel
StrataFlash® Wireless Memory (L18) allows burst reads that cross partition boundaries. User
application code is responsible for ensuring that burst reads do not cross into a partition that is
programming or erasing.
Upon initial power up or return from reset, the device defaults to asynchronous page-mode read.
Configuring the Read Configuration Register enables synchronous burst-mode reads. In
synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT
signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the Intel StrataFlash® Wireless Memory
(L18) incorporates technology that enables fast factory program and erase operations. Designed for
low-voltage systems, the Intel StrataFlash® Wireless Memory (L18) supports read operations with
VCC at 1.8 volt, and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced
Factory Programming (Buffered EFP) provides the fastest flash array programming performance
with VPP at 9.0 volt, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be
tied together for a simple, ultra-low power design. In addition to voltage flexibility, a dedicated
VPP connection provides complete data protection when VPP is less than VPPLK.
A Command User Interface (CUI) is the interface between the system processor and all internal
operations of the Intel StrataFlash® Wireless Memory (L18). An internal Write State Machine
(WSM) automatically executes the algorithms and timings necessary for block erase and program.
A Status Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each erase
operation erases one block. The Erase Suspend feature allows system software to pause an erase
cycle to read or program data in another block. Program Suspend allows system software to pause
programming to read other locations. Data is programmed in word increments.
The Intel StrataFlash® Wireless Memory (L18) offers power savings through Automatic Power
Savings (APS) mode and standby mode. The device automatically enters APS following read-cycle
completion. Standby is initiated when the system deselects the device by deasserting CE# or by
asserting RST#. Combined, these features can significantly reduce power consumption.
The Intel StrataFlash® Wireless Memory (L18)’s protection register allows unique flash device
identification that can be used to increase system security. Also, the individual Block Lock feature
provides zero-latency block locking and unlocking.
Datasheet
Intel StrataFlash® Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
11

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