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PDF PCA9600 Data sheet ( Hoja de datos )
| Número de pieza | PCA9600 | |
| Descripción | Dual Bidirectional Bus Buffer | |
| Fabricantes | NXP Semiconductors | |
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PCA9600
Dual bidirectional bus buffer
Rev. 04 — 11 November 2009
Product data sheet
1. General description
The PCA9600 is designed to isolate I2C-bus capacitance, allowing long buses to be driven
in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a
higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic interface
between a normal I2C-bus and a range of other higher capacitance or different voltage
bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side
is compatible with the Fast-mode Plus (Fm+) specifications.
The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface
making it suitable for interfacing with buses that have non I2C-bus-compliant logic levels
such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.
The separation of the bidirectional I2C-bus signals into unidirectional TX and RX signals
enables the SDA and SCL signals to be transmitted via balanced transmission lines
(twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX
signals may be connected together to provide a normal bidirectional signal.
2. Features
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I Bidirectional data transfer of I2C-bus signals
I Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side
I TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive
buses
I 1 MHz operation on up to 20 meters of wire (see AN10658)
I Supply voltage range of 2.5 V to 15 V with I2C-bus logic levels on SX/SY side
independent of supply voltage
I Splits I2C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface
with opto-electrical isolators and similar devices that need unidirectional input and
output signal paths
I Low power supply current
I ESD protection exceeds 4500 V HBM per JESD22-A114, 450 V MM per
JESD22-A115, and 1400 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: SO8 and TSSOP8 (MSOP8)
1 page  
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
Remark: Two or more SX or SY I/Os must not be interconnected. The PCA9600 design
does not support this configuration. Bidirectional I2C-bus signals do not allow any
direction control pin so, instead, slightly different logic LOW voltage levels are used at
SX/SY to avoid latching of this buffer. A ‘regular I2C-bus LOW’ applied at the RX/RY of a
PCA9600 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage
level. If this special ‘buffered LOW’ is applied to the SX/SY of another PCA9600, that
second PCA9600 will not recognize it as a ‘regular I2C-bus LOW’ and will not propagate it
to its TX/TY output. The SX/SY side of PCA9600 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example P82B96, PCA9511A,
PCA9515A, ‘B’ side of PCA9517, etc. The SX/SY side is only intended for, and compatible
with, the normal I2C-bus logic voltage levels of I2C-bus master and slave chips, or even
TX/RX signals of a second PCA9600 or P82B96 if required. The TX/RX and TY/RY I/O
pins use the standard I2C-bus logic voltage levels of all I2C-bus parts. There are no
restrictions on the interconnection of the TX/RX and TY/RY I/O pins to other PCA9600s,
for example in a star or multipoint configuration with the TX/RX and TY/RY I/O pins on the
common bus and the SX/SY side connected to the line card slave devices. For more
details see Application Note AN10658, “Sending I2C-bus signals via long communication
cables”.
The PCA9600 is a direct upgrade of the P82B96 with the significant differences
summarized in Table 4.
Table 4. PCA9600 versus P82B96
Detail
Supply voltage (VCC) range:
Maximum operating bus voltage
(independent of VCC):
Typical operating supply current:
Typical LOW-level input voltage on I2C-bus
(SX/SY side):
www.DLaOtaWSh-leeevte4Ul o.cuotmput voltage on I2C-bus
(SX/SY side; 3 mA sink):
LOW-level output voltage on Fm+ I2C-bus
(SX/SY side; 7 mA sink):
Temperature coefficient of VIL / VOL:
Logic voltage levels on SX/SY bus
(independent of VCC):
Typical propagation delays:
TX/RX switching specifications (I2C-bus
compliant):
RX logic levels with tighter control than
I2C-bus limit of 30 % to 70 %:
Maximum bus speed:
ESD rating HBM per JESD22-A114:
Package:
PCA9600
2.5 V to 15 V
15 V
P82B96
2 V to 15 V
15 V
5 mA
0.5 V over −40 °C to +85 °C
1 mA
0.65 V at 25 °C
0.74 V (max.) over −40 °C to +85 °C 0.88 V (typ.) at 25 °C
1 V (max.)
n/a
0 mV/°C
−2 mV/°C
compatible with I2C-bus and similar compatible with I2C-bus and similar
buses using TTL levels (SMBus, etc.) buses using TTL levels (SMBus, etc.)
< 100 ns
< 200 ns
yes, all classes including 1 MHz Fm+ yes, all classes including Fm+
yes, 40 % to 55 % (48 % nominal) yes, 42 % to 58 % (50 % nominal)
> 1 MHz
> 4500 V
SO8, TSSOP8 (MSOP8)
> 400 kHz
> 3500 V
DIP8, SO8, TSSOP8 (MSOP8)
PCA9600_4
Product data sheet
Rev. 04 — 11 November 2009
© NXP B.V. 2009. All rights reserved.
5 of 30
5 Page 
NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
1400
VCC(max)
(mV)
1200
002aac075
1000
800
600
400
−50 −25
0
25 50 75 100 125
Tj (°C)
Fig 9. VCC bus release limit over temperature;
maximum values
1000
II
(µA)
800
600
(1)
(2)
001aai062
400
200
0
−50 −25
0
25 50 75 100 125
Tj (°C)
(1) Maximum.
(2) Typical.
Fig 10. Current sourced out of SX/SY as a function of
junction temperature if these pins are
externally pulled to 0.4 V or lower
www.DataSheet4U.com
PCA9600_4
Product data sheet
Rev. 04 — 11 November 2009
© NXP B.V. 2009. All rights reserved.
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