PDF ICS84330C Data sheet ( Hoja de datos )

Número de pieza	ICS84330C
Descripción	CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICS84330C 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION ICS The ICS84330C is a general purpose, single out- put high frequency synthesizer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps from 250KHz to 2MHz can be achieved using a 16MHz crystal depending on the output divider setting. FEATURES • Fully integrated PLL, no external loop filter requirements • 1 differential 3.3V LVPECL output • Crystal oscillator interface: 10MHz to 25MHz • Output frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • Parallel or serial interface for programming M and N dividers during power-up • RMS Period jitter: 5ps (maximum) • Cycle-to-cycle jitter: 40ps (maximum) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Pin compatible with the MC12430 • Lead-Free package available • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT OE XTAL1 XTAL2 FREF_EXT OSC XTAL_SEL www.DataSheet4U.com 1 0 ÷ 16 PLL PHASE DETECTOR VCO ÷M ÷2 ÷2 1 ÷4 ÷8 ÷1 0 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 CONFIGURATION INTERFACE LOGIC 25 24 23 22 21 20 19 S_CLOCK S_DATA S_LOAD VCCA FREF_EXT XTAL_SEL XTAL1 26 18 27 ICS84330C 17 28 28-Lead PLCC 16 1 V Package 15 11.6mm x 11.4mm x 4.1mm 2 body package 14 3 Top View 13 4 12 N1 N0 M8 M7 M6 M5 M4 FOUT nFOUT 5 6 7 8 9 10 11 TEST S_CLOCK S_DATA S_LOAD VCCA VCCA FREF_EXT XTAL_SEL XTAL1 32 31 30 29 28 27 26 25 1 24 2 23 3 ICS84330C 22 32-Lead LQFP 4 Y package 21 5 7mm x 7mm x 1.4mm 20 6 body package 19 7 Top View 18 8 17 9 10 11 12 13 14 15 16 n/c N1 N0 M8 M7 M6 M5 M4 84330CV www.icst.com/products/hiperclocks.html 1 REV. B DECEMBER 7, 2004 1 page Integrated Circuit Systems, Inc. ICS84330C 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, V I Outputs, IO Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, T STG 4.6V -0.5V to V + 0.5 V CC 50mA 100mA 37.8°C/W (0 lfpm) -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol VCC VCCA ICC ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 160 16 Units V V mA mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH VIL Parameter Input High Voltage Input Low Voltage www.DatIaIHSheet4U.cIonmput High Current I Input Low Current IL M0-M8, N0, N1, OE, nP_LOAD, XTAL_SEL S_LOAD, S_CLOCK FREF_EXT, S_DATA M0-M8, N0, N1, OE, nP_LOAD, XTAL_SEL S_LOAD, S_CLOCK FREF_EXT, S_DATA Test Conditions VCC = VIN = 3.465V V = V = 3.465V CC IN VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 Units V V 5 µA 150 µA -150 µA -5 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 V Peak-to-Peak Output Voltage Swing SWING NOTE 1: Outputs terminated with 50Ω to VCC - 2V. Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 1.0 VCC - 1.7 1.0 Units V V V 84330CV www.icst.com/products/hiperclocks.html 5 REV. B DECEMBER 7, 2004 5 Page Integrated Circuit Systems, Inc. ICS84330C 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C3 and C4, as close as pos- sible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V pin as possible. CCA CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. • The differential 50Ω output traces should have the same length. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. • Make sure no other signal traces are routed between the clock trace pair. • The matching termination resistors should be located as close to the receiver input pins as possible. CRYSTAL The crystal X1 should be located as close as possible to the pins 4 (XTAL1) and 5 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic in- ductance and capacitance. Other signal traces should not be routed near the crystal traces. X1 www.DataSheet4U.com C1 U1 C2 PIN 2 PIN 1 C11 C16 VCCA R7 GND VCC VCCA VIA Signals Traces 84330CV C3 C4 50 Ohm Traces FIGURE 6B. PCB BOARD LAYOUT FOR ICS84330C www.icst.com/products/hiperclocks.html 11 REV. B DECEMBER 7, 2004 11 Page

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