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PDF ICS84330-03 Data sheet ( Hoja de datos )

Número de pieza ICS84330-03
Descripción CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Fabricantes Integrated Circuit Systems 
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Integrated
Circuit
Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS84330-03 is a general purpose, dual
ICS output high frequency synthesizer and a mem-
HiPerClockS™ ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The VCO
operates at a frequency range of 250MHz to
700MHz. The VCO and output frequency can be pro-
grammed using the I2C interface. The output can be config-
ured to divide the VCO frequency by 1, 2, 3, 4, and 6.
Additionally, the device suppor ts spread spectrum clock-
ing (SSC) for minimizing Electromagnetic Interference
(EMI). The low cycle-cycle jitter and broad frequency
range of the ICS84330-03 make it an ideal clock gen-
erator for a variety of demanding applications which
require high performance.
BLOCK DIAGRAM
FEATURES
Fully integrated PLL, no external loop filter requirements
Two differential 3.3V LVPECL output
Crystal oscillator interface: 10MHz to 25MHz
Output frequency range: 41.67MHz to 700MHz
VCO range: 250MHz to 700MHz
Parallel or I2C interface for programming M and N dividers
during power-up
Supports Spread Spectrum Clocking (SSC)
Center spread: selectable ±0.5%, ±1.0%, ±1.5%, ±2%
Up/Down spread: selectable 0.5%, 1.0%, 1.5%, 2%,
2.5%, 3%, 3.5%, 4%
RMS Period jitter: 9ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
OE Pullup
VCO_SEL Pullup
XTAL_IN
OSC
XTAL_OUT
FREF_EXT Pulldown
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XTAL_SEL Pullup
1
0
÷16
PLL
Phase Detector
VCO
÷M ÷2
0
1
÷1 1
÷2 0
SCL
SDA
ADDR_SEL
VCCA
VCCA
FREF_EXT
XTAL_SEL
XTAL_IN
32 31 30 29 28 27 26 25
1 24
2 23
3 ICS84330-03 22
4 32-Lead LQFP 21
Y package
5 7mm x 7mm x 1.4mm 20
6 body package 19
7
Top View
18
8 17
9 10 11 12 13 14 15 16
VCO_SEL
N1
N0
M8
M7
M6
M5
M4
Q0
nQ0
ADDR_SEL Pulldown
SDA
SCL
nP_LOAD Pullup
I2C Parallel Interface
÷2
÷3
1
÷4
÷6 0
Q1
nQ1
M0:M8 M0:M7 = Pulldown, M8 = Pullup
N0 Pulldown
N1 Pulldown
84330AY-03
www.icst.com/products/hiperclocks.html
1
REV. A FEBRUARY 2, 2006

1 page




ICS84330-03 pdf
Integrated
Circuit
Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16.6667MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 7, NOTE 1.
The ICS84330-03 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A quartz crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve lock. The output of the VCO is scaled by a divider
prior to being sent to each of the LVPECL output buffers.
The divider provides a 50% output duty cycle.
The programmable features of the ICS84330-03 support
two input modes to program the M divider and N output
divider. The two input operational modes are parallel and
I2C. Figure 1 shows the timing diagram for parallel mode. In
parallel mode the nP_LOAD input is LOW. The data on
inputs M0 through M8 and N0 through N1 is passed
directly to the M divider and N output divider. On the LOW-
to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW tran-
sition on nP_LOAD or until an I2C event occurs. The rela-
tionship between the VCO frequency, the crystal frequency
and
the
M
divider
is
defined
as
follows: fVCO
=
fxtal
16
x
2M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Func-
tion Table. Valid M values for which the PLL will achieve
lock are defined as 120 M 336. The frequency out is
defined
as
follows:
fout
=
fVCO
N
=
fxtal
16
x
2M
N
PARALLEL LOADING
M0:M8, N0:N1
nP_LOAD
M, N
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Time
FIGURE 1. PARALLEL LOAD OPERATIONS
84330AY-03
www.icst.com/products/hiperclocks.html
5
REV. A FEBRUARY 2, 2006

5 Page





ICS84330-03 arduino
Integrated
Circuit
Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84330-03 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
V
CC
VCCA
3.3V
.01μF 10Ω
.01μF 10μF
FIGURE 2. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
SELECT PINS:
All select pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resistor can be used.
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
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CRYSTAL INPUT INTERFACE
The ICS84330-03 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values, C1 and C2,
shown in Figure 3 below were determined using an 18pF
parallel resonant crystal and were chosen to minimize the
ppm error. These same capacitor values will tune any 18pF
parallel resonant crystal over the frequency range and other
parameters specified in this data sheet. The optimum C1
and C2 values can be slightly adjusted for different board
layouts.
84330AY-03
X1
18pF Parallel Cry stal
XTAL_IN
C1
22p
XTAL_OUT
C2
22p
ICS84332
Figure 3. CRYSTAL INPUt INTERFACE
www.icst.com/products/hiperclocks.html
11
REV. A FEBRUARY 2, 2006

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