PDF XR17V358 Data sheet ( Hoja de datos )

Número de pieza	XR17V358
Descripción	HIGH PERFORMANCE OCTAL PCI EXPRESS UART
Fabricantes	Exar Corporation
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No Preview Available ! PRELIMINARY XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART JULY 2009 REV. P1.0.2 GENERAL DESCRIPTION The XR17V3581 (V358) is a single chip 8-channel PCI Express (PCIe) UART (Universal Asynchronous Receiver and Transmitter), optimized for higher performance and lower power. The V358 serves as a single lane PCIe bridge to 8 indepedent enhanced 16550 compatible UARTs. The V358 is compliant to PCIe 2.0 Gen 1 (2.5GT/s). In addition to the UART channels, the V358 has 16 multi-purpose I/Os (MPIOs), a 16-bit general purpose counter/timer and a global interrupt status register to optimize interrupt servicing. Each UART of the V358 has many enhanced features such as the 256-bytes TX and RX FIFOs, programmable Fractional Baud Rate Generator, Automatic Hardware or Software Flow Control, Auto RS-485 Half-Duplex Direction Control, programmable TX and RX FIFO Trigger Levels, TX and RX FIFO Level Counters, infrared mode, and data rates up to 25Mbps. The V358 is available in a 176-pin FPBGA package (13 x 13 mm). NOTE 1: Covered by U.S. Patents #5,649,122, #6,754,839, #6,865,626 and #6,947,999 APPLICATIONS • Next generation Point-of-Sale Systems • Remote Access Servers • Storage Network Management • Factory Automation and Process Control www.DataS•heMet4uUlt.ic-poomrt RS-232/RS-422/RS-485 Cards FIGURE 1. BLOCK DIAGRAM OF THE XR17V358 FEATURES • Single 3.3V power supply • Internal buck regulator for 1.2V core • PCIe 2.0 Gen 1 compliant • x1 Link, dual simplex, 2.5Gbps in each direction • Expansion bus interface • EEPROM interface for configuration • Data read/write burst operation • Global interrupt status register for all eight UARTs • Up to 25 Mbps serial data rate • 16 multi-purpose inputs/outputs (MPIOs) • 16-bit general purpose timer/counter • Sleep mode with wake-up Indicator • Eight independent UART channels controlled with ■ 16550 compatible register Set ■ 256-byte TX and RX FIFOs ■ Programmable TX and RX Trigger Levels ■ TX/RX FIFO Level Counters ■ Fractional baud rate generator ■ Automatic RTS/CTS or DTR/DSR hardware flow control with programmable hysteresis ■ Automatic Xon/Xoff software flow control ■ RS-485 half duplex direction control output with programmable turn-around delay ■ Multi-drop with Auto Address Detection ■ Infrared (IrDA 1.1) data encoder/decoder • Software compatible to XR17C15x, XR17D15x, XR17V25x PCI UARTs TX+ TX- RX+ RX- CLK+ CLK- CLKREQ# PERST# EN485# E N IR # EECK EEDI EEDO EECS D [7:0] SEL CLK IN T MODE PRES C o n fig u ratio n Space R eg isters PInCtPIeCLr foIaeccael Bus In te rfa c e C o n fig u ratio n EREeSPgpiRascOt eeMr s In te rfa c e E xp an sio n In te rfac e B uck R egulator 125 M H z C lo ck G lobal C onfiguration R egisters 16- b it T im er/C o u n ter UART Channel 0 UART Regs 26546- - b y t e T X F IF O TTXX && RR XX IR ENDEC B R G 26546- - bbyyttee RRXX FFIIFFOO UART Channel 1 UART Channel 2 UART Channel 3 UART Channel 4 UART Channel 5 UART Channel 6 UART Channel 7 MMuullttii-- p u r p o s e In p u ts/O u tp u ts C rystal O sc/B uffer TT XX [[ 77 :: 00 ]] R X [7:0] RRTTSS##[[77::00]] DDTTRR##[[77::00]] C T S #[7:0] D S R #[7:0] D C D #[7:0] R I#[7:0] M MP IPOIO[ 1[57::00]] TM RCK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page REV. P1.0.2 PIN DESCRIPTIONS NAME CTS5# DTR5# PIN # B3 B2 DSR5# CD5# RI5# TX6 RX6 C3 B1 C2 R7 P8 RTS6# CTS6# DTR6# DSR6# CD6# RI6# TX7 RX7 P7 R9 P9 N9 R10 P10 N10 P11 RTS7# www.DataSheet4UC.cToSm7# DTR7# R11 N11 P12 DSR7# R13 CD7# M11 RI7# N12 EXPANSION INTERFACE MODE G15 CLK G14 D7 F15 PRELIMINARY XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART TYPE DESCRIPTION I UART channel 5 Clear to Send or general purpose input (active LOW). O UART channel 5 Data Terminal Ready or general purpose output (active LOW). I UART channel 5 Data Set Ready or general purpose input (active LOW). I UART channel 5 Carrier Detect or general purpose input (active LOW). I UART channel 5 Ring Indicator or general purpose input (active LOW). O UART channel 6 Transmit Data or infrared transmit data. I UART channel 6 Receive Data or infrared receive data. Normal RXD input idles at HIGH condition. The infrared pulses can be inverted prior to decoding by setting FCTR bit [4]. O UART channel 6 Request to Send or general purpose output (active LOW). I UART channel 6 Clear to Send or general purpose input (active LOW). O UART channel 6 Data Terminal Ready or general purpose output (active LOW). I UART channel 6 Data Set Ready or general purpose input (active LOW). I UART channel 6 Carrier Detect or general purpose input (active LOW). I UART channel 6 Ring Indicator or general purpose input (active LOW). O UART channel 7 Transmit Data or infrared transmit data. I UART channel 7 Receive Data or infrared receive data. Normal RXD input idles at HIGH condition. The infrared pulses can be inverted prior to decoding by setting FCTR bit [4]. O UART channel 7 Request to Send or general purpose output (active LOW). I UART channel 7 Clear to Send or general purpose input (active LOW). O UART channel 7 Data Terminal Ready or general purpose output (active LOW). I UART channel 7 Data Set Ready or general purpose input (active LOW). I UART channel 7 Carrier Detect or general purpose input (active LOW). I UART channel 7 Ring Indicator or general purpose input (active LOW). I Expansion Interface Mode Select. Connect this pin to VCC to enable master mode or when there is no slave device. Connect this pin to GND when the device is in slave mode. I/O Expansion Interface Clock. In master mode, this pin is the clock output to the slave device. In slave mode, this pin is the clock input from the master device. The expansion interface clock is 62.5MHz. The UARTs on the slave device will need to use different baud rate generator divisors than the master device. I/O Expansion Interface Data 7 (MSB) 5 5 Page REV. P1.0.2 ADDRESS OFFSET BITS 0x00 31:16 0x04 15:0 31 30 29:28 27 26:25 24 23 22 21 20 19:16 15:11, 9,7, 5, 4, 3, 2 10 www.DataSheet4U.com 8 6 1 0 0x08 0x0C 0x10 31:8 7:0 31:24 23:16 15:8 7:0 31:14 13:0 PRELIMINARY XR17V358 HIGH PERFORMANCE OCTAL PCI EXPRESS UART TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS TYPE DESCRIPTION EWR EWR RWC RWC RO RO RO RO RO RO RO RO RO RO Device ID - No slave device on expansion interface Device ID - XR17V358 slave device on expansion interface Device ID - XR17V354 slave device on expansion interface Vendor ID (Exar) specified by PCISIG Parity error detected. Cleared by writing a logic 1. System error detected. Cleared by writing a logic 1. Unused Target Abort. DEVSEL# timing. Unemployments bus master error reporting bit Fast back to back transactions are supported Reserved Status bit 66MHz capable Capabilities List Reserved Status bits Command bits (reserved) RESET VALUE (HEX OR BINARY) 0x0358 0x8358 0x4358 0x13A8 0b 0b 00b 0b 00b 0b 0b 0b 0b 1b 0000b 0x0000 RWR RWR RWR RWR RO EWR RO RO RO RO RO RWR RO This bit disables the device from asserting INTx#. logic 1 = dis- able assertion of INTx# and logic 0 = enables assertion of INTx# 0b SERR# driver enable. logic 1=enable driver and 0=disable driver 0b Parity error enable. logic 1=respond to parity error and 0=ignore 0b Command controls a device’s response to mem space accesses: 0=disable mem space accesses, 1=enable mem space accesses 0b Device’s response to I/O space accesses is disabled. (0 = disable I/O space accesses) 0b Class Code (Default is ’Simple 550 Communication Controller’) 0x070002 Revision ID (Exar device revision number) Current Rev. value BIST (Built-in Self Test) 0x00 Header Type (a single function device with one BAR) 0x00 Unimplemented Latency Timer (needed only for bus master) 0x00 Unimplemented Cache Line Size 0x00 Memory Base Address Register (BAR0) 0x00000 Claims an 16K address space for the memory mapped UARTs including the UARTs on the expansion interface. 0x0000 11 11 Page

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