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PDF XR17V354 Data sheet ( Hoja de datos )
| Número de pieza | XR17V354 | |
| Descripción | HIGH PERFORMANCE QUAD PCI-EXPRESS UART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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PRELIMINARY
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
JULY 2009
REV. P1.0.2
GENERAL DESCRIPTION
The XR17V3541 (V354) is a single chip 4-channel
PCI Express (PCIe) UART (Universal Asynchronous
Receiver and Transmitter), optimized for higher
performance and lower power. The V354 serves as a
single lane PCIe bridge to 4 indepedent enhanced
16550 compatible UARTs. The V354 is compliant to
PCIe 2.0 Gen 1 (2.5GT/s).
In addition to the UART channels, the V354 has 16
multi-purpose I/Os (MPIOs), a 16-bit general purpose
counter/timer and a global interrupt status register to
optimize interrupt servicing.
Each UART of the V354 has many enhanced
features such as the 256-bytes TX and RX FIFOs,
programmable Fractional Baud Rate Generator,
Automatic Hardware or Software Flow Control, Auto
RS-485 Half-Duplex Direction Control, programmable
TX and RX FIFO Trigger Levels, TX and RX FIFO
Level Counters, infrared mode, and data rates up to
25Mbps. The V354 is available in a 176-pin FPBGA
package (13 x 13 mm).
NOTE 1: Covered by U.S. Patents #5,649,122, #6,754,839,
#6,865,626 and #6,947,999
APPLICATIONS
• Next generation Point-of-Sale Systems
• Remote Access Servers
• Storage Network Management
• Factory Automation and Process Control
www.DataS•heMet4uUlt.ic-poomrt RS-232/RS-422/RS-485 Cards
FIGURE 1. BLOCK DIAGRAM OF THE XR17V354
FEATURES
• Single 3.3V power supply
• Internal buck regulator for 1.2V core
• PCIe 2.0 Gen 1 compliant
• x1 Link, dual simplex, 2.5Gbps in each direction
• Expansion bus interface
• EEPROM interface for configuration
• Data read/write burst operation
• Global interrupt status register for all four UARTs
• Up to 25 Mbps serial data rate
• 16 multi-purpose inputs/outputs (MPIOs)
• 16-bit general purpose timer/counter
• Sleep mode with wake-up Indicator
• Four independent UART channels controlled with
■ 16550 compatible register Set
■ 256-byte TX and RX FIFOs
■ Programmable TX and RX Trigger Levels
■ TX/RX FIFO Level Counters
■ Fractional baud rate generator
■ Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
■ Automatic Xon/Xoff software flow control
■ RS-485 half duplex direction control output
with programmable turn-around delay
■ Multi-drop with Auto Address Detection
■ Infrared (IrDA 1.1) data encoder/decoder
• Software compatible to XR17C15x, XR17D15x,
XR17V25x PCI UARTs
TX+
TX-
RX+
RX-
CLK+
CLK-
CLKREQ#
PERST#
EN485#
E N IR #
EECK
EEDI
EEDO
EECS
D [7:0]
SEL
CLK
IN T
MODE
PRES
C o n fig u ratio n
Space
R eg isters
B uck R egulator
PInCtPIeCLr foIaeccael
Bus
In te rfa c e
C o n fig u ratio n
EREeSPgpiRascOt eeMr s
In te rfa c e
125 M H z C lo ck
G lobal
C onfiguration
R egisters
E xp an sio n
In te rfac e
16- b it
T im er/C o u n ter
UART Channel 0
UART
Regs
26546- - b y t e T X F IF O
TTXX && RR XX
IR
ENDEC
B R G 26546- - bbyyttee RRXX FFIIFFOO
UART Channel 1
UART Channel 2
U A R T C h a n n e l 32
UART Channel 3
UART Channel 5
UART Channel 6
M u lti-p u rp o se
IUnAp uRtTs /COhuatpn un tesl 7
- purpose
In p u ts/O u tp u ts
C rystal O sc/B uffer
TT XX [[ 37 :: 00 ]]
R X [3:0]
R X [7:0]
R TS#[3:0]
D T R #[3:0]
C T S #[3:0]
D S R #[3:0]
D C D #[3:0]
R I#[3:0]
M P IO [15:0]
TM RCK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. P1.0.2
PIN DESCRIPTIONS
NAME
SEL
PIN #
G13
INT D14
PRES
H14
MPIO SIGNALS
MPIO0
MPIO1
MPIO2
MPIO3
MPIO4
MPIO5
MPIO6
www.DataSheet4UM.cPoImO7
MPIO8
MPIO9
MPIO10
MPIO11
MPIO12
MPIO13
MPIO14
C1
D2
D1
E3
E2
E1
F3
L3
M2
N1
P1
M3
N2
P2
M4
PRELIMINARY
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
TYPE
DESCRIPTION
I/O Expansion Interface Read/Write Select. This is the the read/write select input
in the slave mode. This is the read/write select output in the master mode.
This pin must be left unconnected if there is no slave device.
I/O Expansion Interface Interrupt. This is the expansion interface interrupt output
in the slave mode. This is the expansion interface interrupt input in the mas-
ter mode. This pin must be left unconnected if there is no slave device.
I Slave Present. In master mode, connect this pin to VCC if there is a slave
device present. Connect this pin to GND to disable access to the slave
device (slave device may or may not be present). In slave mode, this pin
should be connected to GND.
I/O Multi-purpose input/output 0. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
I/O Multi-purpose input/output 1. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 2. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 3. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 4. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 5. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 6. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 7. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 8. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
I/O Multi-purpose input/output 9. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 10. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 11. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 12. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 13. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
I/O Multi-purpose input/output 14. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
5
5 Page 
REV. P1.0.2
ADDRESS
OFFSET
BITS
0x10 31:14
13:0
0x14
0x18h
0x1C
0x20
0x24
0x28
0x2C
31:0
31:0
31:0
31:0
31:0
31:0
31:16
15:0
0x30 31:0
0x34 31:8
7:0
0x38 31:0
0x3C 31:24
23:16
15:8
www.DataSheet4U.com
0x40
7:0
31:0
0x44 31:0
0x48 31:0
0x4C 31:0
0x50 31:16
15:8
7:0
0x54-0x67 31:0
0x68 31:16
15:8
7:0
0x6C-0x77 31:0
PRELIMINARY
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)
RWR Memory Base Address Register (BAR0)
0x00000
RO Claims an 16K address space for the memory mapped UARTs
including the UARTs on the expansion interface.
0x0000
RWR Unimplemented Base Address Register (returns zeros)
0x00000000
RO Unimplemented Base Address Register (returns zeros)
0x00000000
RO Unimplemented Base Address Register (returns zeros)
0x00000000
RO Unimplemented Base Address Register (returns zeros)
0x00000000
RO Unimplemented Base Address Register (returns zeros)
0x00000000
RO Reserved
0x00000000
EWR Subsystem ID (write from external EEPROM by customer)
0x0000
EWR
Subsystem Vendor ID (write from external EEPROM by cus-
tomer)
0x0000
RO Expansion ROM Base Address (Unimplemented)
0x00000000
RO Reserved (returns zeros)
0x000000
RO Capability Pointer
0x50
RO Reserved (returns zeros)
0x00000000
RO Unimplemented MAXLAT
0x00
RO Unimplemented MINGNT
0x00
RO Interrupt Pin, use INTA#.
0x01
RWR Interrupt Line.
0xXX
RO Not implemented or not applicable (return zeros)
0x00000000
RO CSR
0x02106160
RO Not implemented or not applicable (return zeros)
0x00000000
RO Not implemented or not applicable (return zeros)
0x00000000
RO 64-bit address capable
0x0080
RO Next Capability Pointer
0x78
RO MSI Capable Capability ID
0x05
RO Not implemented or not applicable (return zeros)
0x00000000
RO Not implemented or not applicable (return zeros)
0x0000
RO Next Capability Pointer
0x78
RO MSI-X Capable Capability ID
0x11
RO Not implemented or not applicable (return zeros)
0x00000000
11
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| PDF Descargar | [ Datasheet XR17V354.PDF ] | |
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