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PDF PCA9306 Data sheet ( Hoja de datos )
| Número de pieza | PCA9306 | |
| Descripción | Dual bidirectional I2C-bus and SMBus voltage-level translator | |
| Fabricantes | NXP Semiconductors | |
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PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Rev. 04 — 26 October 2009
Product data sheet
1. General description
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The PCA9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an
enable (EN) input, and is operational from 1.0 V to 3.6 V (Vref(1)) and 1.8 V to 5.5 V
(Vbias(ref)(2)).
The PCA9306 allows bidirectional voltage translations between 1.0 V and 5 V without the
use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections
to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,
and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,
allowing bidirectional data flow between ports. When EN is LOW, the translator switch is
off, and a high-impedance state exists between ports.
The PCA9306 is not a bus buffer like the PCA9509 or PCA9517A that provide both level
translation and physically isolates the capacitance to either side of the bus when both
sides are connected. The PCA9306 only isolates both sides when the device is disabled
and provides voltage level translation when active.
The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency
and the other at 100 kHz operating frequency. If the two buses are operating at different
frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other
bus is required. If the master is running at 400 kHz, the maximum system operating
frequency may be less than 400 kHz because of the delays added by the translator.
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector
configuration of the I2C-bus. The size of these pull-up resistors depends on the system,
but each side of the translator must have a pull-up resistor. The device is designed to work
with Standard-mode, Fast-mode and Fast mode Plus I2C-bus devices in addition to
SMBus devices. The maximum frequency is dependent on the RC time constant, but
generally supports > 2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the
voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a seamless
translation between higher and lower voltages selected by the user without the need for
directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
1 page  
NXP Semiconductors
PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
5.2 Pin description
Table 2.
Symbol
GND
VREF1
SCL1
SDA1
SDA2
SCL2
VREF2
EN
Pin description
Pin
SO8,
VSSOP8 (DC)
TSSOP8 (MSOP8),
TSSOP8,
VSSOP8 (DC1),
XQFN8
14
21
32
43
55
66
77
88
Description
ground (0 V)
low-voltage side reference supply voltage for
SCL1 and SDA1
serial clock, low-voltage side; connect to
VREF1 through a pull-up resistor
serial data, low-voltage side; connect to VREF1
through a pull-up resistor
serial data, high-voltage side; connect to
VREF2 through a pull-up resistor
serial clock, high-voltage side; connect to
VREF2 through a pull-up resistor
high-voltage side reference supply voltage for
SCL2 and SDA2
switch enable input; connect to VREF2 and
pull-up through a high resistor
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PCA9306_4
Product data sheet
Rev. 04 — 26 October 2009
© NXP B.V. 2009. All rights reserved.
5 of 23
5 Page 
NXP Semiconductors
PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Table 10. Pull-up resistor values
Calculated for VOL = 0.35 V; assumes output driver VOL = 0.175 V at stated current.
Vpu(D)
Pull-up resistor value (Ω)
15 mA
10 mA
3 mA
Nominal
+10 %[1]
Nominal
+10 %[1]
Nominal
+10 %[1]
5V
310
341
465
512
1550
1705
3.3 V 197 217 295 325 983 1082
2.5 V 143 158 215 237 717 788
1.8 V 97 106 145 160 483 532
1.5 V
77
85 115 127 383 422
1.2 V
57
63
85
94 283 312
[1] +10 % to compensate for VCC range and resistor tolerance.
11.2.1 Maximum frequency calculation
The maximum frequency is totally dependent upon the specifics of the application and the
device can operate > 33 MHz. Basically, the PCA9306 behaves like a wire with the
additional characteristics of transistor device physics and should be capable of performing
at higher frequencies if used correctly.
Here are some guidelines to follow that will help maximize the performance of the device:
• Keep trace length to a minimum by placing the PCA9306 close to the processor.
• The trace length should be less than half the time of flight to reduce ringing and
reflections.
• The faster the edge of the signal, the higher the chance for ringing.
• The higher the drive strength (up to 15 mA), the higher the frequency the device can
use.
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In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side is being driven by a totem pole type
driver no pull-up resistor is needed on the 3.3 V side. The capacitance and line length of
concern is on the 1.8 V side since it is driven through the ON resistance of the PCA9306.
If the line length on the 1.8 V side is long enough there can be a reflection at the
chip/terminating end of the wire when the transition time is shorter than the time of flight of
the wire because the PCA9306 looks like a high-impedance compared to the wire. If the
wire is not too long and the lumped capacitance is not excessive the signal will only be
slightly degraded by the series resistance added by passing through the PCA9306. If the
lumped capacitance is large the rise time will deteriorate, the fall time is much less
affected and if the rise time is slowed down too much the duty cycle of the clock will be
degraded and at some point the clock will no longer be useful. So the principle design
consideration is to minimize the wire length and the capacitance on the 1.8 V side for the
clock path. A pull-up resistor on the 1.8 V side can also be used to trade a slower fall time
for a faster rise time and can also reduce the overshoot in some cases.
PCA9306_4
Product data sheet
Rev. 04 — 26 October 2009
© NXP B.V. 2009. All rights reserved.
11 of 23
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