PDF CAT5270 Data sheet ( Hoja de datos )

Número de pieza	CAT5270
Descripción	DPP
Fabricantes	ON Semiconductor
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No Preview Available ! CAT5270 Dual Digitally Programmable Potentiometers (DPPt) with 256 Taps & I2C Compatible Interface Description The CAT5270 is a volatile 256−tap by two channels, digitally programmable potentiometer (DPPt) with an I2C compatible interface. Each DPP consists of a linear taper series of resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. On power up the wiper position goes to mid scale. The CAT5270 can be used as a potentiometer or as a two terminal, variable resistor. It is available in a 14−lead TSSOP package operating over the industrial temperature range (−40°C to 85°C). Features • Two Linear Taper Digitally Programmable Potentiometers • 256 Resistor Taps per Potentiometer • End to End Resistance 50 kW, 100 kW • I2C Compatible Interface • Low Wiper Resistance 75 W (typ.) • 2.5 V to 5.5 V Operation • Standby Current Less than 1 mA • Power On to Mid Scale • 14−lead TSSOP Package • Industrial Temperature Range www.DataSheet4U.com RH0 RH1 SDA SCL I2C 256−POSITION COMPATIBLE DECODE INTERFACE CONTROL RW0 RW1 A0 A1 CONTROL A2 LOGIC A3 RL0 RL1 Figure 1. Functional Diagram http://onsemi.com 1 TSSOP−14 Y SUFFIX CASE 948AM PIN CONNECTION A0 VCC RLO RHO RWO A2 SDA 1 TSSOP−14 (Y) (Top View) A3 SCL GND RW1 RH1 RL1 A1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 3 1 Publication Order Number: CAT5270/D 1 page CAT5270 tF tHIGH tR tLOW tLOW SCL tSU:STA SDA IN tHD:STA tHD:DAT tSU:DAT SDA OUT tAA tDH tSU:STO tBUF Figure 2. Bus Timing Serial Bus Protocol The following defines the features of the I2C compatible interface protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5270 will be considered a slave device in all applications. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH (see Figure 3). The CAT5270 monitors the SDA and SCL lines and will not respond until this condition is met. www.DataSheet4U.com STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition (see Figure 3). All operations must end with a STOP condition. Device Addressing The bus Master begins a transmission by sending a START condition. The Master then sends the Slave Addres Byte which contains the address of the particular slave device it is requesting. The four most significant bits of the 8−bit slave address are fixed as 0101 for the CAT5270. The next four significant bits (A3, A2, A1, A0) are the device address bits and define which device the Master is accessing (see Figure 5). Up to sixteen devices may be individually addressed by the system. Typically, +5 V (VCC) and ground are hard−wired to these pins to establish the device’s address. After the Master sends a START condition and the slave address byte, the CAT5270 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. Slave Address Byte The most significant four bits of the slave address are a device type identifier. These bits for the CAT5270 are fixed at 0101[B] (refer to Figure 5). The next four bits, A3 − A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 − A0 input pins for the CAT5270 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 − A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data (see Figure 4). The CAT5270 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte. When the CAT5270 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5270 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. If the device has been selected with an IN/DEC operation it will no longer responds with acknoleadge as the received data it is not in a byte format. http://onsemi.com 5 5 Page

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