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PDF FSBS15CH60 Data sheet ( Hoja de datos )
| Número de pieza | FSBS15CH60 | |
| Descripción | Smart Power Module | |
| Fabricantes | Fairchild Semiconductor | |
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FSBS15CH60
Smart Power Module
March 2005
SPM TM
Features
• UL Certified No.E209204(SPM27-BA package)
• 600V-15A 3-phase IGBT inverter bridge including control ICs
for gate driving and protection
• Divided negative dc-link terminals for inverter current sensing
applications
• Single-grounded power supply due to built-in HVIC
• Isolation rating of 2500Vrms/min.
• Very low leakage current due to using ceramic substrate
Applications
• AC 100V ~ 253V three-phase inverter drive for small power
ac motor drives
• Home appliances applications like air conditioner and wash-
ing machine.
General Description
It is an advanced smart power module (SPMTM) that Fairchild
has newly developed and designed to provide very compact
and high performance ac motor drives mainly targeting low-
power inverter-driven application like air conditioner and wash-
ing machine. It combines optimized circuit protection and drive
matched to low-loss IGBTs. System reliability is further
enhanced by the integrated under-voltage lock-out and short-
circuit protection. The high speed built-in HVIC provides opto-
coupler-less single-supply IGBT gate driving capability that fur-
ther reduce the overall size of the inverter system design. Each
phase current of inverter can be monitored separately due to
the divided negative dc terminals.
Top View
44mm
Bottom View
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26.8mm
Figure 1.
©2005 Fairchild Semiconductor Corporation
FSBS15CH60 Rev. B
1
www.fairchildsemi.com
1 page  
Absolute Maximum Ratings (TJ = 25°C, Unless Otherwise Specified)
Inverter Part
Symbol
Parameter
Conditions
Rating
Units
VPN
VPN(Surge)
VCES
± IC
± ICP
PC
TJ
Supply Voltage
Supply Voltage (Surge)
Collector-emitter Voltage
Each IGBT Collector Current
Each IGBT Collector Current (Peak)
Collector Dissipation
Operating Junction Temperature
Applied between P- NU, NV, NW
Applied between P- NU, NV, NW
TC = 25°C
TC = 25°C, Under 1ms Pulse Width
TC = 25°C per One Chip
(Note 1)
450
500
600
15
30
32
-20 ~ 125
V
V
V
A
A
W
°C
Note:
1. The maximum junction temperature rating of the power chips integrated within the SPM is 150 °C(@TC ≤ 100°C). However, to insure safe operation of the SPM, the average
junction temperature should be limited to TJ(ave) ≤ 125°C (@TC ≤ 100°C)
Control Part
Symbol
Parameter
Conditions
Rating Units
VCC Control Supply Voltage
Applied between VCC(UH), VCC(VH), VCC(WH), VCC(L) -
COM
20
V
VBS High-side Control Bias
Voltage
Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) -
VS(W)
20 V
VIN Input Signal Voltage
Applied between IN(UH), IN(VH), IN(WH), IN(UL), IN(VL),
IN(WL) - COM
-0.3~17
V
VFO Fault Output Supply Voltage Applied between VFO - COM
-0.3~VCC+0.3
V
IFO Fault Output Current
Sink Current at VFO Pin
5 mA
VSC Current Sensing Input Voltage Applied between CSC - COM
-0.3~VCC+0.3
V
Total System
Symbol
Parameter
VPN(PROT) Self Protection Supply Voltage Limit
(Short Circuit Protection Capability)
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TSTG
VISO
Module Case Operation Temperature
Storage Temperature
Isolation Voltage
Conditions
VCC = VBS = 13.5 ~ 16.5V
TJ = 125°C, Non-repetitive, less than 2µs
-20°C≤ TJ ≤ 125°C, See Figure 2
60Hz, Sinusoidal, AC 1 minute, Connection
Pins to ceramic substrate
Rating
400
-20 ~ 100
-40 ~ 125
2500
Units
V
°C
°C
Vrms
Thermal Resistance
Symbol
Parameter
Conditios
Rth(j-c)Q
Rth(j-c)F
Junction to Case Thermal Inverter IGBT part (per 1/6 module)
Resistance
Inverter FWD part (per 1/6 module)
Note:
2. For the measurement point of case temperature(TC), please refer to Figure 2.
Min.
-
-
Typ.
-
-
Max. Units
3.1 °C/W
3.6 °C/W
FSBS15CH60 Rev. B
5
www.fairchildsemi.com
5 Page 
CPU
5V-Line
RPF=
4.7kΩ
100 Ω
1nF
C PF=
1nF
SPM
IN(UH) , IN (VH) , IN(W H)
IN (UL) , IN (VL) , IN(WL)
VFO
COM
Note:
1. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s
printed circuit board. The SPM input signal section integrates 3.3kΩ (typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the sig-
nal voltage drop at input terminal.
2. The logic input is compatible with standard CMOS or LSTTL outputs.
Figure 9. Recommended CPU I/O Interface Circuit
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These Values depend on PW M Control Algorithm
15V-Line
RBS
DBS
22uF
0.1uF
RE(H)
One-Leg Diagram of SPM
Vcc VB
IN HO
COM VS
P
1000uF
1uF
Vcc
IN OUT
COM VSL
Inverter
Output
N
Note:
1. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
2. The bootstrap resistor (RBS) should be 3 times greater than RE(H). The recommended value of RE(H) is 5.6Ω, but it can be increased up to 20Ω (maximum) for a slower dv/dt of
high-side.
3. The ceramic capacitor placed between VCC-COM should be over 1uF and mounted as close to the pins of the SPM as possible.
Figure 10. Recommended Bootstrap Operation Circuit and Parameters
FSBS15CH60 Rev. B
11
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| PDF Descargar | [ Datasheet FSBS15CH60.PDF ] | |
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