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PDF DS1842A Data sheet ( Hoja de datos )

Número de pieza DS1842A
Descripción Bias Output Stage
Fabricantes Maxim Integrated Products 
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19-4994; Rev 0; 10/09
EVAALVUAAILTAIOBNLEKIT
76V, APD, Bias Output Stage with
Current Monitoring
General Description
The DS1842A integrates the discrete high-voltage
components necessary for avalanche photodiode
(APD) bias and monitor applications. A switch FET and
precision voltage-divider network are used in conjunc-
tion with an external DC-DC controller to create a boost
DC-DC converter. A current clamp limits current
through the APD and also features an external shut-
down. The precision voltage-divider network is provid-
ed for precise control of the APD bias voltage. The
device also includes a dual current mirror to monitor
the APD current.
APD Biasing
GPON ONU and OLT
Applications
Features
76V Maximum Boost Voltage
Switch FET
Current Monitor with a Wide 1µA to 2mA Range,
Fast 50ns Time Constant, and 10:1 and 5:1 Ratio
2mA Current Clamp with External Shutdown
Precision Voltage Feedback
Multiple External Filtering Options
3mm x 3mm, 14-Pin TDFN Package with Exposed Pad
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS1842AN+
-40°C to +85°C 14 TDFN-EP*
DS1842AN+T&R -40°C to +85°C 14 TDFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
Typical Application Circuit
3.3V
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SW
FB
CCOMP RCOMP
COMP
D2
DS1875
LX
GATE
PGND
FBOUT
FBIN
DS1842A
R1
MIRIN
CURRENT MIRROR
CBULK
R2 MIR1
CLAMP
EP GND
CURRENT
LIMIT
MIROUT
MIR2
ROSA
EXTERNAL MONITOR
APD
TIA
MON3
NOTE: SEE THE LAYOUT CONSIDERATIONS SECTION.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




DS1842A pdf
TOP VIEW
MIR1 1
MIR2 2
GND 3
FBOUT 4
CLAMP 5
GATE 6
PGND 7
*EXPOSED PAD.
76V, APD, Bias Output Stage with
Current Monitoring
Pin Configuration
Block Diagram
DS1842A
*EP
TDFN
14 MIROUT
13 MIRIN
12 FBIN
11 N.C.
10 N.C.
9 N.C.
8 LX
FBOUT
LX
GATE
PGND
CLAMP
DS1842A
R1
R2
CURRENT MIRROR
CURRENT
LIMIT
THERMAL
SHUTDOWN
FBIN
MIRIN
MIR1
MIR2
EP GND
MIROUT
PIN
1
2
3
4
5
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7
8
9, 10, 11
12
13
14
NAME
MIR1
MIR2
GND
FBOUT
CLAMP
GATE
PGND
LX
N.C.
FBIN
MIRIN
MIROUT
EP
Pin Description
FUNCTION
Current Mirror Monitor Output, 10:1 Ratio
Current Mirror Monitor Output, 5:1 Ratio
Ground Connection for Device. Connect directly to ground plane. Connect GND to PGND at a
single point. See the Layout Considerations section for more information.
Feedback Output. Resistor-divider output.
Clamp Input. Disables the current mirror output (MIROUT).
FET Gate Connection
Source of Switch FET. Also connect to boost converter’s input and output capacitors. Connect
PGND to GND at a single point. See the Layout Considerations section for more information.
FET Drain Connection. Connect to switching inductor.
No Connection
Feedback Input. Resistor-divider input.
Current Mirror Input
Current Mirror Output. Connect to APD bias pin.
Exposed Pad. Connect directly to the same ground plane as GND.
Detailed Description
The DS1842A contains discrete high-voltage compo-
nents required to create an APD bias voltage and to
monitor the APD bias current. The device’s mirror out-
puts are a current that is a precise ratio of the output
current across a large dynamic range. The mirror
response time is fast enough to comply with GPON Rx
burst-mode monitoring requirements. The device has a
built-in current-limiting feature to protect APDs. The
APD current can also be shut down by CLAMP or ther-
mal shutdown. The internal FET and resistor-divider are
used in conjunction with a DC-DC boost controller to
precisely create the APD bias voltage.
Current Mirror
The DS1842A has two current mirror outputs. One is a
10:1 mirror connected at MIR1, and the other is a 5:1
mirror connected to MIR2.
_______________________________________________________________________________________ 5

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