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PDF IPM6210A Data sheet ( Hoja de datos )
| Número de pieza | IPM6210A | |
| Descripción | Precision Dual PWM Controller And Linear Regulator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM
Data Sheet
IPM6210A
August 2001
File Number 9033.1
Precision Dual PWM Controller And
Linear Regulator for Notebook CPUs
The IPM6210A is a highly integrated power controller which
provides a complete power management solution for mobile
CPUs. The IC integrates two PWM controllers and a linear
regulator as well as monitoring and protection circuitry into a
single 28-lead plastic SSOP package. The two PWM
controllers regulate the microprocessor core and I/O
voltages with synchronous-rectified buck converters, while
the linear regulator powers the CPU clock.
The IPM6210A includes 5-bit digital-to-analog converter
(DAC) that adjusts the core PWM output voltage from
0.925VDC to 2.0VDC and conforms to the Intel Mobile VID
specification. The DAC setting may be changed during
operation to accommodate Dual-Mode processors. Special
measures are taken to provide such a transition with
controlled rate in a specified 100µs. A precision reference,
remote sensing, and a proprietary architecture with
integrated processor mode-compensated “droop” provide
excellent static and dynamic core voltage regulation. The
second PWM controller has a fixed 1.5V output voltage and
powers the I/O circuitry. Both PWM controllers have
integrated feedback loop compensation that dramatically
reduces number of the external components. At nominal
loads PWM controllers operate at a fixed frequency of
300kHz. At light loads when the filter inductor current
becomes discontinuous, controllers operate in a hysteretic
mode. Out-of-phase operation of two PWM controllers to
reduce input current ripple is provide in both modes of
www.oDpaetarSahtioeent.4TUh.ceomlinear regulator uses an internal pass device
to provide 2.5V for the CPU clock generator.
The IPM6210A monitors all the output voltages. A single
Power-Good signal is issued when soft start is completed
and all outputs are within ±10% of their respective set points.
A built-in overvoltage protection for the core and I/O outputs
forces the lower MOSFETs on to prevent output voltages
from going above 115% of their settings. Undervoltage
protection latches the chip off when any of three outputs
drops below 75% of the set value. The PWM controller's
overcurrent circuitry monitors the output current by sensing
the voltage drop across the lower MOSFETs. If precision
overcurrent protection is required, an external current-sense
resistor may optionally be used.
Ordering Information
PART NUMBER TEMP. (oC)
PACKAGE
IPM6210ACA
-10 to 85 28 Ld SSOP
IPM6210ACA-T
-10 to 85 28 Ld SSOP,
Tape and Reel
PKG. NO.
M28.15
M28.15
Features
• Provides 3 Regulated Voltages
- 0.9V to 2.0V Microprocessor Core (SpeedStepTM
Enabled)
- 1.5V Microprocessor I/O
- 2.5V Microprocessor Clock Generator
• High Efficiency Over Wide Load Range
• Not Dissipative Current-Sense Scheme
- Uses MOSFET’s rDS(ON)
- Optional Current-Sense Resistor for Precision
Overcurrent
• Adaptive Dead-Time Drivers for N-Channel MOSFETs
• Operates from +5V, +3.3V and Battery (5.6-24V) Inputs
• Precision Core Voltage Control:
- Remote “Kelvin” Sensing
- Summing Current-Mode Control
- On-Chip Mode-Compensated “Droop” for Optimum
Transient Response and Lower Processor Power
Dissipation
• TTL-Compatible 5-Bit Digital Output Voltage Selection
- Wide Range - 0.925VDC to 1.3VDC in 25mV Steps, and
from 1.3VDC to 2.0VDC in 50mV Steps
- Programmable “On-the-Fly” VID Code Change with
Customer Programmable Slew Rate and 100µs Settling
Time
• Power-Good Output Voltage Monitor
• No Negative Voltage on Outputs at Turn-Off
• Overvoltage, Undervoltage and Overcurrent Fault
Monitors
• 300kHz Fixed Switching Frequency
• Thermal Shutdown
Applications
• Mobile PCs
• Web Tablets
• Internet Appliances
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
SpeedStep™ is a trademark of Intel Corporation. | Copyright © Intersil Americas Inc. 2001, All Rights Reserved
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small addition of the clock frequency pulses. Synchronization of
the upper MOSFET turn-on pulses with the main clock enables
seamless transition between the operation modes.
Operation During Processor Mode Changes
The PWM1 controller is specially designed to provide “on the
fly” automatic core voltage changes required by some
advanced processors for mobile applications. Dual core
voltage and operation frequency scaling allows for significant
power savings without sacrificing system performance in
battery operation mode.
As processor mode changes can happen when chip is in
PWM or hysteretic mode, measures were taken to provide
equally fast response to these changes. As soon as a DAC
code change is received, the chip is forced into PWM mode
till transition completes regardless of the load level.
Operating the controller in the synchronous PWM mode
allows faster output voltage transitions especially when a
downward output voltage change is commanded.
I/O Converter Architecture
The I/O converter architecture is close to that of the core
converter. It has the same mode control logic and can operate
in a constant frequency PWM mode or in hysteretic mode
depending on the load level, but its structure is much simpler
mainly because of absence of the differential input amplifier and
the DAC. This controller is synchronized to the same clock as
the core converter, but 180 degrees out-of-phase. Thus, some
reduction of the input current ripple is achieved.
Some performance curves of I/O converter are shown on
Figure 9 and Figure 10.
Gate Control Logic
The gate control logic translates generated PWM signals into
the MOSFETs gate drive signals providing necessary
www.aDmatpalSifhiceaetito4nU,.cleovmel shift and shoot-trough protection. Also, it
helps to optimize the IC performance over a wide range of the
operational conditions. As MOSFET switching time can very
dramatically from type to type and with input voltage variation,
the gate control logic provides adaptive dead time by
monitoring gate voltages of both upper and lower MOSFETs.
Protections
All three outputs are monitored and protected against extreme
overload, short circuit and undervoltage conditions. Both PWM
outputs are monitored and protected from overvoltage
conditions. A sustained overload on any output latches-off all
the converters and sets the PGOOD pin low. The chip
operation can be restored by cycling VCC voltage or EN pin.
Overcurrent Protection
Both PWM controllers use the lower MOSFET’s
on-resistance - rDS(ON) to monitor the current for protection
against shorted outputs. The sensed voltage drop after
amplification is compared with an internally set threshold.
Several scenarios of the current protection circuit behavior
are possible.
VIO
1
IIO
2
Ch1 50mV
Ch2 500mA
M50ms
FIGURE 9. I/O CONVERTER LOAD TRANSIENT IN PWM MODE
VIO
1
IIO
2
Ch1 50mV
Ch2 500mA
M50µs
FIGURE 10. I/O CONVERTER LOAD TRANSIENT WITH MODE
CHANGE
If load step is strong enough to pull output voltage lower
than the undervoltage threshold, chip shuts down. If the
output voltage sag does not reach the undervoltage
threshold but the current exceeds the overcurrent
threshold, the pulse skipping circuit is activated. This
breaks the output voltage regulation and limits the current
supplied to the load.
Because of the nature of the current sensing technique,
and to accommodate a wide range of the rDS(ON) variation,
the value of the threshold should represent overload
current about 180% of the nominal value. To decrease
current protection circuit noise susceptibility, a time delay
circuit (8:1 counter which counts the clock cycles) is
activated when the overcurrent condition is detected for the
first time. If after the delay the overcurrent condition
persists, the converter shuts down. If not - normal operation
is restored.
11
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