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PDF EL5421T Data sheet ( Hoja de datos )

Número de pieza EL5421T
Descripción 12MHz Rail-to-Rail Input-Output Buffer
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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®
Data Sheet
September 25, 2009
EL5421T
FN6922.0
12MHz Rail-to-Rail Input-Output Buffer
The EL5421T is a high voltage rail-to-rail input-output buffer
with low power consumption. The EL5421T contains four
buffers. Each buffer exhibits beyond the rail input capability,
rail-to-rail output capability and is unity gain stable.
The maximum operating voltage range is from 4.5V to 19V. It
can be configured for single or dual supply operation, and
typically consumes only 500µA per buffer. The EL5421T has
an output short circuit capability of ±200mA and a
continuous output current capability of ±70mA.
The EL5421T features a slew rate of 12V/µs. Also, the
device provides common mode input capability beyond the
supply rails, rail-to-rail output capability, and a bandwidth of
12MHz (-3dB). This enables the buffers to offer maximum
dynamic range at any supply voltage. These features make
the EL5421T an ideal buffer solution for use in TFT-LCD
panels as a VCOM or static gamma buffer, and in high speed
filtering and signal conditioning applications. Other
applications include battery power and portable devices,
especially where low power consumption is important.
The EL5421T is available in a space saving 10 Ld MSOP
package and operates over an ambient temperature range
of -40°C to +85°C.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-Free)
www.DEaLt5a4S2h1eTeIYt4ZU*.com BBBLA
10 Ld MSOP
PKG.
DWG. #
M10.118A
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• 12MHz -3dB bandwidth
• 4 Unity Gain Buffers
• 4.5V to 19V Maximum Supply Voltage Range
• 12V/µs Slew Rate
• 500µA Supply Current (per buffer)
• ±70mA Continuous Output Current
• ±200mA Output Short Circuit Current
• Unity-gain Stable
• Beyond the Rails Input Capability
• Rail-to-rail Output Swing
• Built-in Thermal Protection
• -40°C to +85°C Ambient Temperature Range
• Pb-free (RoHS compliant)
Applications
• TFT-LCD Panels
• VCOM Buffers
• Electronics Notebooks
• Electronics Games
• Personal Communication Devices
• Personal Digital Assistants (PDA)
• Portable Instrumentation
• Wireless LANs
• Office Automation
• Active Filters
• ADC/DAC Buffers
Pinout
EL5421T
(10 LD MSOP)
TOP VIEW
VOUTA 1
VINA 2
VS+ 3
VINB 4
VOUTB 5
10 VOUTD
9 VIND
8 VS-
7 VINC
6 VOUTC
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Elantec is a registered trademark of Elantec Semiconductor, Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




EL5421T pdf
EL5421T
Typical Performance Curves
2200
2000
1800
1600
VS = ±5V
TA = +25°C
TYPICAL
PRODUCTION
DISTRIBUTION
1400
1200
1000
800
600
400
200
0 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
INPUT OFFSET VOLTAGE (mV)
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
28
24
VS = ±5V
-40°C TO +85°C
20
TYPICAL
PRODUCTION
DISTRIBUTION
16
12
8
4
0 1 3 5 7 9 11 13 15
INPUT OFFSET VOLTAGE DRIFT (|µV|/°C)
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
10
VS = ±5V
5
0
-5
-50
0 50 100
TEMPERATURE (°C)
150
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
2
VS = ±5V
1
0
-1
-2
-50
0 50 100
TEMPERATURE (°C)
150
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
4.95
www.DataSheet4U.com
4.93
VS = ±5V
IOUT = 5mA
4.91
4.89
-50
0 50 100
TEMPERATURE (°C)
150
FIGURE 5. OUTPUT HIGH VOLTGE vs TEMPERATURE
-4.91
-4.92
VS = ±5V
IOUT= -5mA
-4.93
-4.94
-4.95
-4.96
-50
0 50 100
TEMPERATURE (°C)
150
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
5 FN6922.0
September 25, 2009

5 Page





EL5421T arduino
EL5421T
phase margin and the stability of the EL5421T. The
advantage of a snubber circuit is that it does not draw any
DC load current or reduce the gain.
Another method to reduce peaking is to add a series output
resistor (typically between 1Ω to 10Ω). Depending on the
capacitive loading, a small value resistor may be the most
appropriate choice to minimize any reduction in gain.
Power Dissipation
With the high-output drive capability of the EL5421T buffers,
it is possible to exceed the +150°C absolute maximum
junction temperature under certain load current conditions. It
is important to calculate the maximum power dissipation of
the EL5421T in the application. Proper load conditions will
ensure that the EL5421T junction temperature stays within a
safe operating region.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
PDMAX = T----J---M-----A----X-Θ----–-J---A-T----A---M-----A----X--
(EQ. 1)
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
ΘJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation allowed
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply
voltage, plus the power dissipation in the IC due to the loads,
or:
www.DPaDtMaSAhXee=t4ΣUi[.cVoSm× ISMAX + (V S+ VOUTi ) × ILOADi ] (EQ. 2)
when sourcing, and:
PDMAX = Σi[VS × ISMAX + (VOUTi VS- ) × ILOADi ]
(EQ. 3)
when sinking.
Where:
• i = 1 to 4
(1, 2, 3, 4 corresponds to Channel A, B, C, D respectively)
• VS = Total supply voltage (VS+ - VS-)
• VS+ = Positive supply voltage
• VS- = Negative supply voltage
• ISMAX = Maximum supply current per buffer
(ISMAX = EL5421T quiescent current ÷ 4)
• VOUT = Output voltage
• ILOAD = Load current
Device overheating can be avoided by calculating the
minimum resistive load condition, RLOAD, resulting in the
highest power dissipation. To find RLOAD set the two PDMAX
equations equal to each other and solve for VOUT/ILOAD.
Reference the package power dissipation curves, Figures 27
and 28, for further information.
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
8
7 625mW
6
5
MSOP10
θJA = +200°C/W
4
3
2
1
0
0 25 50 75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE
1.0 THERMAL CONDUCTIVITY TEST BOARD
0.9
781mW
0.8
0.7
0.6
MSOP10
θJA = +160°C/W
0.5
0.4
0.3
0.2
0.1
0.0
0
25 50 75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
11 FN6922.0
September 25, 2009

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