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PDF UPD46128512-X Data sheet ( Hoja de datos )

Número de pieza UPD46128512-X
Descripción 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
Fabricantes NEC 
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
μPD46128512-X
128M-BIT CMOS MOBILE SPECIFIED RAM
8M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
Description
The μPD46128512-X is a high speed, low power, 134,217,728 bits (8,388,608 words by 16 bits) CMOS Mobile
Specified RAM featuring asynchronous page read and random write, synchronous burst read/write function.
The μPD46128512-X is fabricated with advanced CMOS technology using one-transistor memory cell.
Features
8,388,608 words by 16 bits organization
Asynchronous page read mode
Synchronous read and write mode
Burst length: 8 words / 16 words / continuous
Clock latency: 5, 6, 7, 8, 9, 10
Burst sequence: Linear burst
Max clock frequency: 108/83 MHz
Byte data control: /LB (DQ0 to DQ7), /UB (DQ8 to DQ15)
Low voltage operation: 1.7 to 2.0 V
Operating ambient temperature: TA = 30 to +85 °C
Chip Enable input: /CE1 pin
Standby Mode input: CE2 pin
Standby Mode 1: Normal standby (Memory cell data hold valid)
Standby Mode 2: Density of memory cell data hold is variable
μPD46128512 Clock Asynchronous Operating Operating
www.DataSheet4U.com frequency initial access supply ambient At operating
MHz
time
voltage temperature
mA
(MAX.)
ns
V °C (MAX.)
Supply current
At standby μA
(MAX.)
(TYP.)
Density of data hold
Density of data hold
(MAX.)
128M 32M 16M 8M 0M 128M 32M 16M 8M 0M
bits bits bits bits bits bits bits bits bits bits
-E9X Note
-E10X Note
108
70 1.7 to 2.0 30 to +85 60 250 T.B.D. T.B.D. T.B.D. 65 80 T.B.D. T.B.D. T.B.D. 15
85 50
-E11X
83 70
60
-E12X
85
50
Note Under consideration
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M17507EJ2V0DS00 (2nd edition)
Date Published September 2005 CP (K)
Printed in Japan
The mark shows major revised points.
2005

1 page




UPD46128512-X pdf
μ PD46128512-X
Truth Table
Asynchronous Operation
Mode
/CE1 CE2 /ADV /OE /WE /LB /UB DQ /WAIT
DQ0 to DQ7 DQ8 to DQ15
Not selected (Standby Mode 1)
HH× × × × ×
Not selected (Standby Mode 2) Note1
×
L
×
×
×
×
×
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Word read
Lower byte read
L H Note3 L H L L
LH
DOUT
DOUT
DOUT
High-Z
High-Z
High-Z
Upper byte read
HL
High-Z
DOUT
High-Z
Output disable
HH
High-Z
High-Z
High-Z
Output disable
H
××
High-Z
High-Z
High-Z
Word write
LLL
DIN
DIN High-Z
Lower byte write
LH
DIN
High-Z
High-Z
Upper byte write
Abort write Note2
HL
HH
High-Z
High-Z
DIN
High-Z
High-Z
High-Z
Notes 1. CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition).
2. If /WE = LOW and /LB = /UB = HIGH, memory does not accept write data, so write operation is not available.
3. Fixed LOW or toggle HIGH LOW HIGH
Remark H, HIGH : VIH, L, LOW : VIL, ×: VIH or VIL
Clock pin must be fixed either LOW or HIGH.
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Preliminary Data Sheet M17507EJ2V0DS
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UPD46128512-X arduino
μ PD46128512-X
2. Partial Refresh
2.1 Standby Mode
In addition to the regular standby mode (Standby Mode 1) with a 128M bits density, Standby Mode 2, which performs
partial refresh, is also provided.
2.2 Density Switching
In Standby Mode 2, the densities that can be selected for performing refresh are 32M bits, 16M bits, 8M bits, and 0M
bit.
The density for performing refresh can be set with the mode register. Once the refresh density has been set in the
mode register, these settings are retained until they are set again, while applying the power supply. However, the mode
register setting will become undefined if the power is turned off, so set the mode register again after power application.
(For how to perform mode register settings, refer to section 5. Mode Register Settings.)
2.3 Standby Mode Status Transition
In Standby Mode 1, /CE1 and CE2 are HIGH. In Standby Mode 2, CE2 is LOW. In Standby Mode 2, if 0M bit is set as
the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal
operation from Standby Mode 2. When the density has been set to 32M bits, 16M bits, or 8M bits in Standby Mode 2, it is
not necessary to perform initialization to return to normal operation from Standby Mode 2.
For the timing charts, refer to Figure 10-1. Standby Mode 2 Entry / Exit Timing Chart (Asynchronous Mode),
Figure 10-2. Standby Mode 2 (data not held) Entry / Exit Timing Chart (Asynchronous Mode).
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Preliminary Data Sheet M17507EJ2V0DS
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