|
|
PDF EDD5116AGTA-4 Data sheet ( Hoja de datos )
| Número de pieza | EDD5116AGTA-4 | |
| Descripción | 512M bits DDR SDRAM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de EDD5116AGTA-4 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
DATA SHEET
512M bits DDR SDRAM
EDD5108AGTA-4 (64M words × 8 bits)
EDD5116AGTA-4 (32M words × 16 bits)
Specifications
• Density: 512M bits
• Organization
⎯ 16M words × 8 bits × 4 banks (EDD5108AGTA)
⎯ 8M words × 16 bits × 4 banks (EDD5116AGTA)
• Package: 66-pin plastic TSOP (II)
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 2.5V ± 0.125V
• Data rate: 500Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
⎯ Sequential (2, 4, 8)
⎯ Interleave (2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge option for each burst
access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
⎯ Average refresh period: 7.8μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
www.DataSheet4U.com
Document No. E1195E20 (Ver. 2.0)
Date Published February 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2007-2008
1 page  
EDD5108AGTA-4, EDD5116AGTA-4
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–1.0 to +3.6
–1.0 to +3.6
50
1.0
0 to +70
–55 to +125
Unit Note
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0°C to +70°C)
Parameter
Symbol
min.
typ.
max.
Unit Notes
Supply voltage
Input reference voltage
VDD, VDDQ
VSS,
VSSQ
VREF
2.375
0
0.49 × VDDQ
2.5
0
0.50 × VDDQ
2.625
0
0.51 × VDDQ
V
V
V
1
Termination voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
—
VDDQ + 0.3
V
2
Input low voltage
VIL (DC)
–0.3
—
VREF – 0.15
V
3
Input voltage level,
CK and /CK inputs
VIN (DC)
–0.3
—
VDDQ + 0.3
V
4
Input differential cross point
voltage, CK and /CK inputs
VIX
0.5 × VDDQ − 0.2V 0.5 × VDDQ
0.5 × VDDQ + 0.2V V
Input differential voltage,
CK and /CK inputs
VID (DC)
0.36
—
VDDQ + 0.6
V
5, 6
www.DataSNhoeteet4sU: 1.c.omVDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC excursion of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Data Sheet E1195E20 (Ver. 2.0)
5
5 Page 
Block Diagram
CK
/CK
CKE
A0 to A12, BA0, BA1
/CS
/RAS
/CAS
/WE
www.DataSheet4U.com
EDD5108AGTA-4, EDD5116AGTA-4
Mode
register
Row
address
buffer
and
refresh
counter
Bank 3
Bank 2
Bank 1
Memory cell array
Bank 0
Column
address
buffer
and
burst
counter
CK, /CK
DLL
Sense amp.
Column decoder
Data control circuit
Latch circuit
Input & Output buffer
DQ
DQS
DM
Data Sheet E1195E20 (Ver. 2.0)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EDD5116AGTA-4.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| EDD5116AGTA-4 | 512M bits DDR SDRAM | Elpida Memory |
| EDD5116AGTA-4 | 512M bits DDR SDRAM | Elpida Memory |
| EDD5116AGTA-LI | 512M bits DDR SDRAM WTR | Elpida Memory |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |