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PDF EDD5116AFTA-5 Data sheet ( Hoja de datos )
| Número de pieza | EDD5116AFTA-5 | |
| Descripción | 512M bits DDR SDRAM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
512M bits DDR SDRAM
EDD5108AFTA-5 (64M words × 8 bits, DDR400)
EDD5116AFTA-5 (32M words × 16 bits, DDR400)
Description
The EDD5108AFTA and the EDD5116AFTA are 512M
bits Double Data Rate (DDR) SDRAM organized as
16,777,216 words × 8 bits × 4 banks and 8,388,608
words × 16 bits × 4 banks, respectively. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. They are
packaged in standard 66-pin plastic TSOP (II).
Features
• Power supply: VDD ,VDDQ = 2.6V ± 0.1V
• Data rate: 400Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
www.DataShetreatn4sUi.tcioonms
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 3
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
• TSOP (II) package with lead free solder (Sn-Bi)
RoHS compliant
Pin Configurations
/xxx indicates active low signal.
VDD VDD
DQ0 DQ0
VDDQ VDDQ
NC DQ1
DQ1 DQ2
VSSQ VSSQ
NC DQ3
DQ2 DQ4
VDDQ VDDQ
NC DQ5
DQ3 DQ6
VSSQ VSSQ
NC DQ7
NC NC
VDDQ VDDQ
NC LDQS
NC NC
VDD VDD
NC NC
NC LDM
/WE /WE
/CAS /CAS
/RAS /RAS
/CS /CS
NC NC
BA0 BA0
BA1 BA1
A10(AP) A10(AP)
A0 A0
A1 A1
A2 A2
A3 A3
VDD VDD
66-pin Plastic TSOP(II)
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
VSS VSS
DQ15 DQ7
VSSQ VSSQ
DQ14 NC
DQ13 DQ6
VDDQ VDDQ
DQ12 NC
DQ11 DQ5
VSSQ VSSQ
DQ10 NC
DQ9 DQ4
VDDQ VDDQ
DQ8 NC
NC NC
VSSQ VSSQ
UDQS DQS
NC NC
VREF VREF
VSS VSS
UDM DM
/CK /CK
CK CK
CKE CKE
NC NC
A12 A12
A11 A11
A9 A9
A8 A8
A7 A7
A6 A6
A5 A5
A4 A4
VSS VSS
X 16
X8
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, LDM, UDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0741E20 (Ver. 2.0)
Date Published October 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
1 page  
EDD5108AFTA-5, EDD5116AFTA-5
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V)
max.
Parameter
Symbol Grade × 8
× 16 Unit Test condition
Notes
Operating current (ACT-
PRE)
IDD0
120
120
mA
CKE ≥ VIH,
tRC = tRC (min.)
1, 2, 9
Operating current
(ACT-READ-PRE)
IDD1
160
160
mA
CKE ≥ VIH, BL = 4,CL = 3,
tRC = tRC (min.)
1, 2, 5
Idle power down standby
current
IDD2P
5 5 mA CKE ≤ VIL
4
Floating idle standby current IDD2F
30
30
mA
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
4, 5
Quiet idle standby current IDD2Q
25
25
mA
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
4, 10
Active power down standby
current
IDD3P
30 30 mA CKE ≤ VIL
3
Active standby current
IDD3N
60
60
mA
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
3, 5, 6
Operating current
(Burst read operation)
IDD4R
215 215 mA CKE ≥ VIH, BL = 2, CL = 3 1, 2, 5, 6
Operating current
(Burst write operation)
IDD4W
215 215 mA CKE ≥ VIH, BL = 2,CL = 3 1, 2, 5, 6
Auto Refresh current
IDD5
220
220
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Self refresh current
IDD6
5
5
mA
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Operating current
(4 banks interleaving)
IDD7A
400 400 mA BL = 4
1, 5, 6, 7
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at ≥ VIH or ≤ VIL.
www.DataSDhCeeCt4hUa.croamcteristics 2 (TA = 0°C to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V)
Parameter
Symbol min.
max.
Unit Test condition
Notes
Input leakage current
Output leakage current
Output high current
Output low current
ILI –2
ILO –5
IOH –15.2
IOL 15.2
2
5
—
—
µA VDD ≥ VIN ≥ VSS
µA VDDQ ≥ VOUT ≥ VSS
mA VOUT = 1.95V
mA VOUT = 0.35V
Data Sheet E0741E20 (Ver. 2.0)
5
5 Page 
EDD5108AFTA-5, EDD5116AFTA-5
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A9, and A11 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command
cycle. This column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Part number
Row address
Column address
EDD5108AFTA
AX0 to AX12
AY0 to AY9, AY11
EDD5116AFTA
AX0 to AX12
AY0 to AY9
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write
command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
www.DataSBhaenekt4US.ecloemct Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Data Sheet E0741E20 (Ver. 2.0)
11
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| PDF Descargar | [ Datasheet EDD5116AFTA-5.PDF ] | |
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