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PDF EDD5108ADTA-LI Data sheet ( Hoja de datos )
| Número de pieza | EDD5108ADTA-LI | |
| Descripción | 512M bits DDR SDRAM WTR | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
512M bits DDR SDRAM
WTR (Wide Temperature Range)
EDD5108ADTA-LI (64M words × 8 bits)
EDD5116ADTA-LI (32M words × 16 bits)
Description
The EDD5108AD and the EDD5116AD are 512M bits
Double Data Rate (DDR) SDRAM. Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 2 bits prefetch-pipelined architecture. Data
strobe (DQS) both for read and write are available for
high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable.
Features
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data Rate: 333Mbps/266Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
www.DataShetreatn4sUi.tcioonms
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
• Ambient temperature range: −40 to +85°C
Pin Configurations
/xxx indicates active low signal.
VDD VDD
DQ0 DQ0
VDDQ VDDQ
NC DQ1
DQ1 DQ2
VSSQ VSSQ
NC DQ3
DQ2 DQ4
VDDQ VDDQ
NC DQ5
DQ3 DQ6
VSSQ VSSQ
NC DQ7
NC NC
VDDQ VDDQ
NC LDQS
NC NC
VDD VDD
NC NC
NC LDM
/WE /WE
/CAS /CAS
/RAS /RAS
/CS /CS
NC NC
BA0 BA0
BA1 BA1
A10(AP) A10(AP)
A0 A0
A1 A1
A2 A2
A3 A3
VDD VDD
66-pin Plastic TSOP(II)
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
VSS VSS
DQ15 DQ7
VSSQ VSSQ
DQ14 NC
DQ13 DQ6
VDDQ VDDQ
DQ12 NC
DQ11 DQ5
VSSQ VSSQ
DQ10 NC
DQ9 DQ4
VDDQ VDDQ
DQ8 NC
NC NC
VSSQ VSSQ
UDQS DQS
NC NC
VREF VREF
VSS VSS
UDM DM
/CK /CK
CK CK
CKE CKE
NC NC
A12 A12
A11 A11
A9 A9
A8 A8
A7 A7
A6 A6
A5 A5
A4 A4
VSS VSS
X 16
X8
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, LDM, UDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0505E10 (Ver. 1.0)
ThisDate Published March 2004 (K) Japan
product
became
EOL
in
September,
2007.
URL: http://www.elpida.com
Elpida Memory, Inc. 2004
1 page  
EDD5108ADTA-LI, EDD5116ADTA-LI
DC Characteristics 1 (TA = –40 to +85°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
max.
Parameter
Symbol Grade
×8
× 16 Unit Test condition
Operating current
(ACT-PRE)
IDD0
-6B
-7A
150
135
150
135
mA
CKE ≥ VIH,
tRC = tRC (min.)
Operating current
(ACT-READ-PRE)
IDD1
-6B
-7A
200
175
210
180
CKE ≥ VIH, BL = 4,
mA CL = 2.5,
tRC = tRC (min.)
Idle power down standby
current
IDD2P
3 3 mA CKE ≤ VIL
Floating idle standby current IDD2F
-6B
-7A
30
25
30
25
mA
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
Quiet idle standby current IDD2Q
20
20
mA
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
Active power down standby
current
IDD3P
20 20 mA CKE ≤ VIL
Active standby current
IDD3N
-6B
-7A
65
55
65
55
mA
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
Operating current
(Burst read operation)
IDD4R
-6B
-7A
250
210
270
230
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
Operating current
(Burst write operation)
IDD4W
-6B
-7A
250
210
270
230
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
Auto Refresh current
IDD5
-6B
-7A
320
300
320
300
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Self refresh current
(L-version)
IDD6
-XXLI
3
3
mA
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Operating current
(4 banks interleaving)
IDD7A
-6B
-7A
510
430
530
450
mA BL = 4
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
www.DataSheet4U1.c0o.mCommand/Address stable at ≥ VIH or ≤ VIL.
Notes
1, 2, 9
1, 2, 5
4
4, 5
4, 10
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
1, 5, 6, 7
DC Characteristics 2 (TA = –40 to +85°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Symbol min.
max.
Unit Test condition
Note
Input leakage current
Output leakage current
Output high current
Output low current
ILI –2
ILO –5
IOH –15.2
IOL 15.2
2
5
—
—
µA VDD ≥ VIN ≥ VSS
µA VDDQ ≥ VOUT ≥ VSS
mA VOUT = 1.95V
mA VOUT = 0.35V
Data Sheet E0505E10 (Ver. 1.0)
5
5 Page 
EDD5108ADTA-LI, EDD5116ADTA-LI
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A9, A11 and A12 at the cross point of the CK rising edge and the /CK falling edge in a read or a write
command cycle. This column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Part number
Row address
Column address
EDD5108AD
AX0 to AX12
AY0 to AY9, AY11
EDD5116AD
AX0 to AX12
AY0 to AY9
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write
command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
www.DataSBhaenekt4US.ecloemct Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL
Data Sheet E0505E10 (Ver. 1.0)
11
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