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PDF M36P0R8070E0 Data sheet ( Hoja de datos )

Número de pieza M36P0R8070E0
Descripción 256 Mbit Flash memory 128 Mbit (burst) PSRAM
Fabricantes Numonyx 
Logotipo Numonyx Logotipo



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No Preview Available ! M36P0R8070E0 Hoja de datos, Descripción, Manual

M36P0R8070E0
256 Mbit (x16, multiple bank, multilevel, burst) Flash memory
128 Mbit (burst) PSRAM, 1.8 V supply, multichip package
Features
Multichip package
– 1 die of 256 Mbit (16 Mb x 16, multiple
bank, multilevel, burst) Flash memory
– 1 die of 128 Mbit (8 Mb x16) PSRAM
Supply voltage
– VDDF = VCCP = VDDQ = 1.7 to 1.95 V
– VPPF = 9 V for fast program (12 V tolerant)
Electronic signature
– Manufacturer code: 20h
– Device code: 8818
Package
– ECOPACK®
Flash memory
Synchronous/asynchronous read
– Synchronous burst read mode:
108 MHz, 66 MHz
– Asynchronous page read mode
– Random access: 93 ns
Programming time
– 4 µs typical Word program time using
www.DataSheet4UB.cuomffer Enhanced Factory Program
command
Memory organization
– Multiple bank memory array: 32 Mbit banks
– Four EFA (extended flash array) blocks of
64 Kbits
Dual operations
– Program/erase in one bank while read in
others
– No delay between read and write
operations
Security
– 64bit unique device number
– 2112 bit user programmable OTP Cells
100 000 program/erase cycles per block
FBGA
TFBGA107 (ZAC)
Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WPF for block lock-down
– Absolute write protection with VPPF = VSS
CFI (common Flash interface)
PSRAM
Access time: 70 ns
Asynchronous page read
– Page size: 4, 8 or 16 words
– Subsequent read within page: 20 ns
Synchronous burst read/write
Low power consumption
– Active current: < 25 mA
– Standby current: 200 µA
– Deep power-down current: 10 µA
Low power features
– PASR (partial array self refresh)
– DPD (deep power-down) mode
December 2007
Rev 2
1/22
www.numonyx.com
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M36P0R8070E0 pdf
M36P0R8070E0
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TFBGA107 8 x 11 mm 9 x 12 active ball array, 0.8 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
www.DataSheet4U.com
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M36P0R8070E0 arduino
M36P0R8070E0
Signal descriptions
2.11
Flash Deep Power-Down (DPDF)
The deep power-down input put sthe device in deep power-down mode.
When the device is in standby mode and the Enhanced Configuration Register bit ECR15 is
set, asserting the deep power-down input causes the memory to enter deep power-down
mode.
When the device is in the deep power-down mode, the memory cannot be modified and the
data is protected.
The polarity of the DPDF pin is determined by ECR14. The deep power-down input is active
Low by default.
2.12
PSRAM Chip Enable input (EP)
The Chip Enable input activates the PSRAM when driven Low (asserted). When de-
asserted (VIH), the device is disabled, and goes automatically in low-power standby mode or
deep power-down mode, according to the RCR (Refresh Configuration Register) setting.
2.13
PSRAM Write Enable (WP)
Write Enable, WP, controls the bus write operation of the PSRAM. When asserted (VIL), the
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
2.14
PSRAM Output Enable (GP)
When held Low, VIL, the Output Enable, GP, enables the bus read operations of the PSRAM.
2.15 PSRAM Upper Byte Enable (UBP)
www.DataSheet4U.com The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a write or read operation.
2.16
2.17
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a write or read operation.
If both LBP and UBP are disabled (High), the device disables the data bus from receiving or
transmitting data. Although the device seems to be deselected, it remains in an active mode
as long as EP remains Low.
PSRAM Configuration Register Enable (CRP)
When this signal is driven High, VIH, bus read or write operations access either the value of
the RCR or the BCR (Bus Configuration Register) according to the value of A19.
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