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PDF S4405 Data sheet ( Hoja de datos )

Número de pieza S4405
Descripción Bicmos PLL Clock Generators
Fabricantes AMCC 
Logotipo AMCC Logotipo



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DEVICE SPECIFICATION
BiCMOS PECL CLOCK GENERATOR
®
S4405
FEATURES
• Generates six clock outputs from 20 MHz to 80
MHz (HFOUT operates from 10 MHz to 40 MHz)
• Allows PECL or TTL reference input
• Provides differential PECL output at up to 160
MHz
• 21 selectable phase/frequency relationships for
the clock outputs
• Compensates for clock skew by allowing output
delay adjustment down to 3.125 ns increments
• TTL outputs have less than 400 ps maximum
skew
• Lock Detect output indicates loop status
• Internal PLL with VCO operating at 160 to 320
MHz
• Test Enable input allows VCO bypass for open-
loop operation
• Maximum 1.0 ns of phase error (750 ps from
part to part)
• Proven 1.0 micron BiCMOS technology
• Single +5V power supply operation
• 44 PLCC package
APPLICATIONS
• CMOS ASIC Systems
• High-speed Microprocessor Systems
• Backplane Clock Deskew and Distribution
GENERAL DESCRIPTION
The S4405 BiCMOS clock generators allow the user
to generate multiphase TTL clocks in the 10–80 MHz
range with less than 400 ps of skew. Use of a simple
off-chip filter allows an entire 160–320 MHz phase-
locked loop (PLL) to be implemented on-chip. Divide-
by-two and times-two outputs allow the ability to
generate output clocks at half, equal to, or twice the
reference clock input frequency. The reference is se-
lectable to be either TTL or PECL. By using the pro-
grammable divider and phase selector, the user can
select from up to 21 different output relationships.
The outputs can be phase-adjusted in increments as
small as 3.125 ns to tailor the clocks to exact system
requirements.
Implemented in AMCC’s proven 1.0 micron BiCMOS
technology, the S4405 generates six TTL outputs
and one differential PECL output. Output enables are
provided for the various TTL banks, allowing clock
control for board and system tests.
Figure 1. Clock Generator Block Diagram
TTLREF
PECLREFP
www.DataSheet4U.comPECLREFN
INPSEL
I0 MUX
I1 S
14K
REFCLK
FBCLK
PHASE
DETECTOR
CHARGE
PUMP
VCO
Digital
+5V
0V
Analog
+5V
0V
TSTEN
DIVSEL
PHSEL0
PHSEL1
RESET
OUTEN0
OUTEN1
÷2
I0
I1
MUX
SELECT
DIVIDER
AND
PHASE
CONTROL
LOGIC
LOCK
FILTER
PECLP
PECLN
X2FOUT
HFOUT
FOUT0
FOUT1
FOUT2
FOUT3
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Page 1

1 page




S4405 pdf
OUTPUT SELECT MATRIX
S4405
Table 3. Output Select Matrix
Configuration
Select Pins
Number
PHSEL1 PHSEL0
1 00
2 00
3 00
4 01
5 01
6 01
7 01
8 01
9 01
10 1 0
11 1 0
12 1 0
13 1 0
14 1 0
15 1 0
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1
Output Fed Output Phase Relationships
to FBCLK
FOUT0 FOUT1 FOUT2 FOUT3 HFOUT
FOUT0–FOUT3
HFOUT
X2FOUT (÷8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (÷8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (÷8)
FOUT0
FOUT1
FOUT2
FOUT3
HFOUT
X2FOUT (÷8)
00
2(0) 2(0)
0/2 0/2
0Q
–Q 0
–2Q –Q
–3Q –2Q
2(0) 2(Q)
0/2 Q/2
0 –t
t0
–t –2t
–Q –Q–t
2(0) 2(–t)
0/2 –t/2
0t
–t 0
–2t –t
–3t –2t
2(0) 2(t)
0/2 t/2
0
2(0)
0/2
2Q
Q
0
–Q
2(2Q)
2Q/2
t
2t
0
–Q+t
2(t)
t/2
2t
t
0
–t
2(2t)
2t/2
0
2(0)
0/2
3Q
2Q
Q
0
2(3Q)
3Q/2
Q
Q+t
Q–t
0
2(Q)
Q/2
3t
2t
t
0
2(3t)
3t/2
0/2
0
0/4
0/2
–Q/2
–2Q/2
–3Q/2
0
0/4
0/2
t/2
–t/2
–Q/2
0
0/4
0/2
–t/2
–2t/2
–3t/2
0
0/4
÷4 ÷8
X2FOUT
0 2(0)
2(0) 4(0)
0
0 2(0)
–Q 2(–Q)
–2Q 2(–2Q)
–3Q 2(–3Q)
2(0) 4(0)
0
0 2(0)
t 2(t)
–t 2(–t)
–Q 2(–Q)
2(0) 4(0)
0
0 2(0)
–t 2(–t)
–2t 2(–2t)
–3t 2(–3t)
2(0) 4(0)
0
Notes:
1. “0” implies the output is aligned with the reference clock.
2. “t” implies the output lags the reference clock by a minimum phase delay.
3. “Q” implies the output lags the reference clock by 90° of phase.
4. “–t” implies the output leads the reference clock by a minimum phase delay.
5. “–Q” implies the output leads the reference clock by 90° of phase.
www6.D. ataS2(he)”eitm4Upl.iceosmthe output is at twice the frequency of the reference clock.
7. “/2” implies the output is at half the frequency of the reference clock.
8. The PECLN/P Differential PECL output is not affected by the PHSEL inputs.
Legend
Table
entry
TTLREF
0
t
2t
–t
Waveform
–t 0 t 2t
Table
entry
TTLREF
Q
2Q
–Q
Waveform
–90° 0° 90° 180°
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Table
entry
TTLREF
2(0)
0/2
4(0)
0/4
Waveform
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