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PDF RC96V24DP Data sheet ( Hoja de datos )
| Número de pieza | RC96V24DP | |
| Descripción | Single Device Data/Fax Modem Data Pump | |
| Fabricantes | Rockwell | |
| Logotipo |  |
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RC96V24DP
Single Device Data/Fax Modem Data Pump
The Rockwell RC96V24DP is a low power, V.22 bis 2400 bps data/fax modem
data pump in a single VLSI package. The RC2324DPL is identical to the
RC96V24DP except fax modes are not provided. In this document, all
references to the RC96V24DP also apply to the RC2324DPL except for the fax
modes and as otherwise noted.
The modem operates over the public switched telephone network (PSTN), as
well as on point-to-point leased lines.
The modem supports data modes meeting the requirements specified in
CCITT recommendations V.22 bis, V.22, V.23, and V.21, as well as Bell 212A and
Bell 103.
The modem supports fax modes meeting the requirements specified in
CCITT V.29, V.27 ter, and V.21 channel 2 synchronous.
Internal HDLC support eliminates the need for an external serial input/output
(SIO) device or comparable functions in the host controller in products
incorporating error correction and T.30 protocols.
The modem includes two CMOS VLSI functions – a digital signal processor
(DSP) and an integrated analog function (IA). The RC96V24DP integrates these
functions into a single 68-pin plastic leaded chip carrier (PLCC).
Detailed hardware and software interface information is described in the
Designer's Guide (Order No. 822).
Functional Block Diagram
SERIAL
www.DataSheet4U.comI N T E R F A C E
(5)
RC96V24DP
MODEM
DEVICE
2
2
HOST
PARALLEL
BUS
INTERFACE
(17)
4
TELEPHONE
LINE
INTERFACE
SPEAKER
AMPLIFIER
(OPTIONAL)
EYE
PATTERN
GENERATOR
(OPTIONAL)
Product Features
• Single CMOS VLSI device
• Low power requirements
– Single voltage: + 5 Vdc ±5%
– Operating: 300 mW (typical)
– Sleep: 15 mW (typical)
• 2-wire operation
– Full- duplex (FDX) for data modes
– Half-duplex (HDX) for fax modes
• Data configurations:
– V.22 bis, V.22, V.23, V.21
– Bell 212A, Bell 103
• Fax configurations (RC96V24DP):
– V.29, V.27 ter, V.21 Channel 2
• Voice mode
• DTMF detection
• Receive dynamic range: -9 dBm to -43 dBm
• Transmit level: -10 dBm ±1 dB using internal
hybrid circuit; attentuation selectable in 1 dB
steps
• Multi-mode data/fax detection support
• V.22 bis fallback/fall-forward -2400/1200 bps
• Serial data: synchronous and asynchronous
• Parallel data: synchronous (including HDLC)
and asynchronous
• Programmable ring detect
• Programmable dialer
• Programmable tone detect bandpass filters
• Adjustable speaker output to monitor
received signal
• Diagnostics
• Host bus interface memory for
configuration, control, and parallel data;
8086 microprocessor bus compatible
• 5-pin serial data interface; TTL compatible
• Equalization
– Adaptive equalizer in receiver
– Selectable and programmable fixed
compromise equalizers in both receiver
and transmitter
• Loopback configurations
– Local analog, local digital, and remote
digital
• Answer and originate handshake in data
modes
• Training sequences for fax modes
• Leased line operation
D96V24DSA
1 page  
RC96V24DP
Single Device Data/Modem Data Pump
1.0 Functional Description
1.2 Technical Specifications
1.2.4.6 Receive Level
1.2.4.7 Receiver Timing
1.2.4.8 Carrier
Recovery
The receiver satisfies performance requirements for a received line signal from
-9 dBm to -43 dBm. The default RLSD turn-on and RLSD turn-off thresholds are
-43 dBm and -48 dBm, respectively. The RLSD threshold levels are
programmable in DSP RAM.
The modem can track a frequency error up to ±0.03% in the associated transmit
timing source.
The modem can track a frequency offset up to ±7 Hz in the received carrier with
less than a 0.2 dB degradation in bit error rate (BER).
www.DataSheet4U.com
D96V24DSA
1-3
5 Page 
www.DataSheet4U.com
2.0
2.0 Hardware Interface
The modem functional hardware interface signals are shown in Figure 2-1. In this
diagram, any point that is active low is represented by a small circle at the signal
point.
Edge triggered inputs are denoted by a small triangle (e.g., TDCLK). Open-
Collector (open-source or open-drain) outputs are denoted by a small half-circle
(e.g., IRQ). Active low signals are overscored (e.g., POR).
A dock intended to activate logic on its rising edge (low-to-high transition) is
called active low (e.g., RDCLK), while a clock Intended to activate logic on its
falling edge (high-to-low transition) is called active high (e.g., TDCLK). When a
clock input is associated with a small circle, the input activates on a falling edge.
If no circle is shown, the input activates on a rising edge.
The modem pin assignments are shown in Figure 2-2. The pin assignments are
listed by pin number in Table 2-1.
The hardware interface signal functions are summarized by major interface in
Table 2-2.
The digital and analog interface characteristics are defined in Table 2-3 and
Table 2-4, respectively.
D96V24DSA
2-1
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet RC96V24DP.PDF ] | |
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