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PDF FSES0765RG Data sheet ( Hoja de datos )
| Número de pieza | FSES0765RG | |
| Descripción | Green Mode Fairchild Power Switch | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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www.fairchildsemi.com
FSES0765RG
Green Mode Fairchild Power Switch (FPSTM) for
CRT Monitors
Features
• Burst Mode Operation to Reduce the Power Consumption
in Standby Mode
• External Pin for Synchronization
• Wide Operating Frequency Range up to 130kHz
• Internal Startup Circuit
• Low Operating Current (Max:6mA)
• Pulse by Pulse Current Limiting
• Over Voltage Protection (Auto Restart Mode)
• Over Load Protection (Auto Restart Mode)
• Abnormal Over Current Protection (Auto Restart Mode)
• Internal Thermal Shutdown (Auto Restart Mode)
• Under Voltage Lockout
• Internal High Voltage SenseFET (650V)
OUTPUT POWER TABLE(3)
PRODUCT
230VAC ±15%(2)
Open Frame(1)
85-265VAC
Open Frame(1)
FSES0765RG
90 W
70 W
Notes:
1. Maximum practical continuous power in an open frame
design at 50°C ambient.
2. 230 VAC or 100/115 VAC with doubler.
3. The maximum output power can be limited by the junction
temperature
Application
• CRT Monitor
Typical Circuit
Vo
Description
FSES0765RG is a Fairchild Power Switch (FPS) specially
designed for off-line SMPS of CRT monitors with minimal
external components. This device combines a current mode
PWM controller with a high voltage power SenseFET in a single
www.DaptaaSchkeageet4.U.Tcohme PWM controller features an integrated
oscillator to be synchronized with the external sync signal,
under voltage lockout, optimized gate driver and
temperature-compensated precise current sources for the loop
compensation. This device also includes various fault
protection circuits such as over voltage protection, over load
protection, abnormal over current protection and over
temperature protection. Compared with discrete MOSFET and
PWM controller solutions, FPS can reduce total cost,
component count, size and weight while simultaneously
increasing efficiency, productivity and system reliability. This
device is well suited for cost effective CRT-monitor power
supplies.
AC
IN
VSync
FSES0765RG
PWM
Vstr
Drain
GND
VFB Vcc
External Sync signal
Figure 1. Typical Flyback Application
©2005 Fairchild Semiconductor Corporation
Rev.1.0.1
1 page  
FSES0765RG
Electrical Characteristics (Continued)
(Ta=25°C unless otherwise specified)
Parameter
SENSEFET SECTION
Drain-Source Breakdown Voltage
Symbol
BVDSS
Zero Gate Voltage Drain Current
IDSS
Static Drain-source on Resistance
Output Capacitance
RDS(ON)
Coss
UVLO SECTION
Vcc Start Threshold Voltage
VSTART
Vcc Stop Threshold Voltage (Normal operation) VSTOP
Vcc Stop Threshold Voltage (Burst operation) VBSTOP
OSCILLATOR SECTION
Initial Frequency
FOSC
Voltage Stability
FSTABLE
Maximum Duty Cycle
DMAX
Minimum Duty Cycle
DMIN
FEEDBACK SECTION
Feedback Source Current (Normal operation)
IFB
Feedback Source Current (Burst operation)
IBFB
Feedback Voltage Threshold to Stop Switching VOFF
Shutdown Feedback Voltage
VSD
Shutdown Delay Current
www.DataPSRheOetT4EUC.coTmION SECTION
IDELAY
Over Voltage Protection
Over Current Protection Threshold Voltage(1)
Thermal Shutdown Temp(2)
VOVP
VAOCP
TSD
Condition
VGS = 0V, ID = 250μA
VDS = Max, Rating, VGS
= 0V
VDS= 0.8*Max., Rating
VGS = 0V, TC = 85°C
VGS = 10V, ID = 2.3A
VGS = 0V, VDS = 25V,
f = 1MHz
VFB=5V
VFB=5V
VFB=0V
VFB=5
11V ≤ Vcc ≤ 18V
VFB=5
-
VFB = 0V, Vcc=15V
VFB = 0V, Vcc=8.7V
0V ≤ VFB ≤ 0.4V
VFB ≥ 6.9V
VFB = 4V
Vcc ≥ 17V
-
-
Min.
650
-
-
-
-
11
8.5
7
18
0
48
-
0.7
70
0.2
7
1.6
18
0.9
140
Typ. Max. Unit
- -V
- 250 μA
- 300 μA
1.4 1.6 Ω
100 130 pF
12 13
9 9.5
7.5 8
V
V
V
20 22 kHz
1 3%
55 62 %
0 -%
0.9 1.1 mA
100 130 uA
0.3 0.4 V
7.5 8 V
2 2.4 μA
19 20 V
1.0 1.1 V
- - °C
Note:
1. These parameters, although guaranteed in design, are tested only in EDS (wafer test) process.
2. These parameters, although guaranteed in design, are not tested in mass production.
5
5 Page 
FSES0765RG
Functional Description
1. Startup : In previous generations of Fairchild Power
Switches (FPSTM) the Vcc pin had an external start-up
resistor to the DC input voltage line. In this generation the
startup resistor is replaced by an internal high voltage current
source. At startup, an internal high voltage current source
supplies the internal bias and charges the external capacitor
(Cvcc) that is connected to the Vcc pin as illustrated in figure
4. When Vcc reaches 12V, the FPS begins switching and the
internal high voltage current source is disabled. Then, the
FPS continues its normal switching operation and the power
is supplied from the auxiliary transformer winding unless
Vcc goes below the stop voltage of 9V.
CVcc
VDC
2.1 Pulse-by-pulse Current Limit: Because current mode
control is employed, the peak current through the Sense FET
is limited by the inverting input of the PWM comparator
(Vfb*) as shown in figure 5. Assuming that the 0.9mA
current source flows only through the internal resistor (2.5R
+R= 2.8 kΩ), the cathode voltage of diode D2 is about 2.5V.
Since diode D1 is blocked when the feedback voltage (Vfb)
exceeds 2.5V, the maximum voltage of the cathode of D2 is
clamped at this voltage, thus clamping Vfb*. Therefore, the
peak value of the SenseFET current is limited.
2.2 Leading Edge Blanking (LEB) : At the instant the
internal Sense FET is turned on, there usually exists a high
current spike through the Sense FET, caused by primary-side
capacitance and secondary-side rectifier reverse recovery.
Excessive voltage across the Rsense resistor would lead to
incorrect feedback operation in the current mode PWM
control. To counter this effect, the FPS employs a leading
edge blanking (LEB) circuit. This circuit inhibits the PWM
comparator for a short time (TLEB) after the Sense FET is
turned on.
Vcc
3
9V/12V
Vcc good
6 Vstr
Istart
Vref
Internal
Bias
www.DataSheet4U.com
Figure 4. Internal Startup Circuit
Vcc Vref
Idelay
IFB
Vo Vfb
H11A817A
4
CB
OSC
D1 D2
2.5R
KA431
+
Vfb* R
-
SenseFET
Gate
driver
VSD
OLP
Rsense
Figure 5. Pulse Width Modulation (PWM) Circuit
2. Feedback Control : FSES0765RG employs current mode
control, as shown in figure 5. An opto-coupler (such as the
H11A817A) and shunt regulator (such as the KA431) are
typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across the
Rsense resistor plus an offset voltage makes it possible to
control the switching duty cycle. When the reference pin
voltage of the KA431 exceeds the internal reference voltage
of 2.5V, the H11A817A LED current increases, thus pulling
down the feedback voltage and reducing the duty cycle. This
event typically happens when the input voltage is increased
or the output load is decreased.
3. Protection Circuits : The FSES0765RG has several self
protective functions such as over load protection (OLP),
abnormal over current protection (AOCP), over voltage
protection (OVP) and thermal shutdown (TSD). Because
these protection circuits are fully integrated into the IC
without requiring external components, the reliability can be
improved without increasing cost. Once the fault condition
occurs, switching is terminated and the Sense FET remains
off. This causes Vcc to fall. When Vcc reaches the UVLO
stop voltage, 9V, the protection is reset and the internal high
voltage current source charges the Vcc capacitor via the Vstr
pin. When Vcc reaches the UVLO start voltage,12V, the FPS
resumes its normal operation. In this manner, the auto-restart
can alternately enable and disable the switching of the power
Sense FET until the fault condition is eliminated (see figure
6).
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet FSES0765RG.PDF ] | |
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