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PDF LG1600FXH0500 Data sheet ( Hoja de datos )

Número de pieza LG1600FXH0500
Descripción LG1600FXH Clock and Data Regenerator
Fabricantes Agere Systems 
Logotipo Agere Systems Logotipo



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Data Sheet
August 1999
LG1600FXH Clock and Data Regenerator
Figure 1. LG1600FXH Open View
Features
s Integrated clock recovery and data retiming
s Surface-mount package
s Single ECL supply
s Robust FPLL design
s Operation up to BER = 1e–3
s SONET/SDH compatible loss of signal alarm
s High effective Q allows long run lengths
s Jitter tolerance exceeding ITU-T/Bellcore
s Low clock jitter generation: typical <0.005 UI
s Standard and custom data rates
0.50 Gbits/s—5.5 Gbits/s
s Complementary 50 I/Os
Applications
s SONET/SDH receiver terminals and regenerators
OC-12 through OC-96/STM-4 through STM-32
s SONET/SDH test equipment
s Proprietary bit rate systems
s Digital video transmission
s Clock doublers and quadruplers

1 page




LG1600FXH0500 pdf
Data Sheet
August 1999
LG1600FXH Clock and Data Regenerator
Theory of Operation (continued)
A more useful expression of the PLL characteristics is
the following*:
H(s)
=
ωb1 + s--1--τ-
-------------------------------------
s + ωb1 + s--1--τ-
The jitter transfer is now directly expressed in the phys-
ical loop gain pole product, ωb, and the loop filter time
constant, τ. Damping ratio, ς, and natural frequency, ωn,
simply relate to these two parameters as follows:
ς = 0.5 ωbτ
and
ωn = ωn ⁄ τ
For moderate damping ς > 2.5 bτ < 0.1), the –3 dB
bandwidth of the PLL can be approximated by the loop
gain pole product:
JBW ≈ ωb = KdRxKo
while the jitter peaking can be expressed in terms of
the product of PLL bandwidth and loop filter time con-
stant:
H(s) max 1 + ω----1-b---τ-
=
1
+
------------1-------------
R x2 C Kd K o
As the last two expressions make clear, the PLL band-
width is controlled by the value of the external resistor
(see Figure 8), while the peaking depends both on the
resistor value (quadratically) and total loop filter capac-
itance.
* Wolaver, D.H., Phase-Locked Loop Circuit Design, Prentice Hall,
1991.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
10 °C
25 °C
70 °C
50 100 150 200 250
Rx ()
3.6
3.0
2.4
1.8
1.2
0.6
0.0
0
10 °C
25 °C
70 °C
50 100 150 200 250
Rx ()
A. LG1600FXH0622 (Cx = 0.15 µF)
B. LG1600FXH2488 (Cx = 0)
12-3231(F)r.4—12-3232(F)r.4
Figure 8. Jitter Bandwidth vs. External Resistor Value
Lucent Technologies Inc.
5

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LG1600FXH0500 arduino
Data Sheet
August 1999
LG1600FXH Clock and Data Regenerator
Typical Performance Characteristics
LG1600FXH0553
LG1600FXH2488
LG1600FXH4977
Lucent Technologies Inc.
Figure 11. LG1600FXH Typical Eye Patterns
11

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