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PDF FAN73901 Data sheet ( Hoja de datos )
| Número de pieza | FAN73901 | |
| Descripción | Gate-Drive IC | |
| Fabricantes | Fairchild Semiconductor | |
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August 2008
FAN73901
High- and Low-Side, Gate-Drive IC
Features
Floating Channels for Bootstrap Operation to +600V
Typically 2.5A/2.5A Sourcing/Sinking Current Driving
Capability
Common-Mode dv/dt Noise Canceling Circuit
Built-in Under-Voltage Lockout for Both Channels
Matched Propagation Delay for Both Channels
3.3V and 5V Input Logic Compatible
Output In-Phase with Input
Applications
Half-Bridge Driver
HID Lamp Ballast
SMPS
Motor Driver
Description
The FAN73901 is a monolithic high- and low-side gate-
drive IC, which can drive high-speed MOSFETs and
IGBTs that operate up to +600V. It has a buffered output
stage with all NMOS transistors designed for high pulse
current driving capability and minimum cross-conduction.
Fairchild’s high-voltage process and common-mode
noise canceling techniques provide stable operation of
the high-side driver under high dv/dt noise circum-
stances. An advanced level-shift circuit offers high-side
gate driver operation up to VS=-9.8V (typical) for
VBS=15V.
The UVLO circuit prevents malfunction when VDD and
VBS are lower than the specified threshold voltage.
The high current and low output voltage drop feature
make FAN73901 suitable for the switching power supply,
motor driver, and high-power DC-DC converter
applications.
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8-SOP
Ordering Information
Part Number
FAN73901M
FAN73901MX
Package
8-SOP
Operating
Temperature Range
-40°C ~ 125°C
Eco Status
RoHS
Packing Method
Tube
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
FAN73901 • Rev. 1.0.0
www.fairchildsemi.com
1 page  
Electrical Characteristics
VBIAS (VDD, VBS)=15.0V, VS=COM, TA=25°C, unless otherwise specified. The VIL, VIH, and IIN parameters are refer-
enced to COM and are applicable to the respective input signals HIN and LIN. The VO and IO parameters are refer-
enced to COM and VS is applicable to the respective output signals HO and LO.
Symbol
Characteristics
Test Condition
Min. Typ. Max. Unit
POWER SUPPLY SECTION (VDD AND VBS)
VDDUV+ VDD and VBS Supply Under-Voltage
VBSUV+ Positive-Going Threshold
VDDUV- VDD and VBS Supply Under-Voltage
VBSUV- Negative-Going Threshold
VDDUVH VDD and VBS Supply Under-Voltage
VBSUVH Lockout Hysteresis Voltage
ILK Offset Supply Leakage Current
IQBS Quiescent VBS Supply Current
IQDD Quiescent VDD Supply Current
IPBS Operating VBS Supply Current
IPDD Operating VDD Supply Current
LOGIC INPUT SECTION (HIN, LIN)
VB=VS=600V
VIN=0V or 5V
VIN=0V or 5V
fIN=20kHz, rms value
fIN=20kHz, rms value
8.0 8.8 9.8 V
7.4 8.3 9.0 V
0.5 V
50 µA
45 80 µA
75 110 µA
530 640 µA
530 640 µA
VIH Logic "1" Input Voltage
VIL Logic "0" Input Voltage
IIN+ Logic "1" Input Bias Current
IIN- Logic "0" Input Bias Current
RIN Input Pull-Down Resistance
GATE DRIVER OUTPUT SECTION (HO, LO)
VIN=5V
VIN=0V
2.5 V
1.2 V
25 50 µA
1.0 2.0 µA
100 200
KΩ
VOH High-Level Output Voltage, VBIAS-VO
VOL Low-Level Output Voltage, VO
IO+
Output High, Short-Circuit Pulsed
Current(4)
No Load
No Load
1.0 V
35 mV
VO=0V, VIN=5V with PW<10µs 1.8 2.5
A
IO-
Output Low, Short-Circuit Pulsed
Current(4)
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VS
Allowable Negative VS Pin Voltage
HIN Signal Propagation to HO
for
VO=15V, VIN=0V with
PW<10µs
1.8 2.5
A
-9.8 -7.0 V
Note:
4. This parameter guaranteed by design.
Dynamic Electrical Characteristics
VBIAS (VDD, VBS)=15.0V, VS=COM=0V, CL=1000pF and TA=25°C unless otherwise specified.
Symbol
Characteristics
Test Condition
Min. Typ.
ton Turn-on Propagation Delay
toff Turn-off Propagation Delay
MT Delay Matching, HS & LS Turn-on/off
VS=0V
VS=0V
140
140
0
tr Turn-on Rise Time
tf Turn-off Fall Time
25
20
Max.
200
200
50
50
45
Unit
ns
ns
ns
ns
ns
© 2008 Fairchild Semiconductor Corporation
FAN73901 • Rev. 1.0.0
5
www.fairchildsemi.com
5 Page 
Mechanical Dimensions
.
3.81
5
B
4.00
3.80
1.75
4
1.27
0.25 M C B A
LAND PATTERN RE
SEE DETA
C
0.51
0.33
0.10 C
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0.50
0.25
x
45°
GAGE PLANE
0.36
OPTION A - BEVEL E
OPTION B - NO BEVEL
NOTES: UNLESS OTHERWIS
SEATING PLANE
A) THIS PACKAGE CONFO
MS-012, VARIATION AA,
B) ALL DIMENSIONS ARE I
Figure 28. 8-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
FAN73901 • Rev. 1.0.0
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet FAN73901.PDF ] | |
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