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PDF WV3EG128M72EFSR-D3 Data sheet ( Hoja de datos )

Número de pieza WV3EG128M72EFSR-D3
Descripción 1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL
Fabricantes White Electronic Designs 
Logotipo White Electronic Designs Logotipo



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No Preview Available ! WV3EG128M72EFSR-D3 Hoja de datos, Descripción, Manual

White Electronic Designs WV3EG128M72EFSR-D3
ADVANCED*
1GB – 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA
FEATURES
Double-data-rate architecture
DDR266 and DDR333
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply:
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and
166MHz)
184 pin DIMM package
PCB height:
• D3: 29.97mm (1.18")
NOTE: Consult factory for availability of:
• Lead-Free Products
• Vendor source control options
www.DatIandSuhsteriaeltt4emUp.ecroatmure options
DESCRIPTION
The WV3EG128M72EFSR is a 128Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of eighteen
64Mx8 DDR components in FBGA packages mounted on
a 184 Pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
March 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




WV3EG128M72EFSR-D3 pdf
White Electronic Designs WV3EG128M72EFSR-D3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Operating Current
Symbol
IDD0
Operating Current
IDD1
Precharge Power-
Down Standby Current
Idle Standby Current
IDD2P
IDD2F
Active Power-Down
Standby Current
Active Standby Current
IDD3P
IDD3N
Operating Current
Operating Current
IDD4R
IDD4W
Auto Refresh Current
IDD5
wSwelwf R.DefaretsahSChuereretn4tU.com IDD6
Operating Current
IDD7A
Conditions
One device bank; Active - Precharge; tRC=tRC (MIN);
tCK=tCK (MIN); DQ,DM and DQS inputs changing once
per clock cycle; Address and control inputs changing
once every two cycles.
One device bank; Active-Read-Precharge Burst = 2;
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and
control inputs changing once per clock cycle.
All device banks idle; Power-down mode; tCK=tCK (MIN);
CKE=(low)
CS# = High; All device banks idle; tCK=tCK (MIN); CKE
= high; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and DM.
One device bank active; Power-Down mode; tCK (MIN);
CKE=(low)
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
tRC = tRC (MIN)
CKE 0.2V
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address
and control inputs change only during Active Read or
Write commands.
DDR333@
CL=2.5
Max
4140
4680
180
1620
1260
1800
4770
4590
7020
180
9090
DDR266@
CL=2
Max
4140
4680
180
1620
1260
1800
4770
4590
7020
180
9000
DDR266@
CL=2.5
Max
4140
Units
mA
4680 mA
180 rnA
1620 mA
1260 mA
1800 mA
4770 mA
4590 rnA
7020 mA
180 mA
9000 mA
March 2005
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





WV3EG128M72EFSR-D3 arduino
White Electronic Designs WV3EG128M72EFSR-D3
ADVANCED
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency tRCD
tRP
Height*
WV3EG128M72EFSR335D3
166MHz/333Mb/s
2.5
33
29.97 (1.18")
WV3EG128M72EFSR262D3
133MHz/266Mb/s
2
22
29.97 (1.18")
WV3EG128M72EFSR265D3
133MHz/266Mb/s
2.5
33
29.97 (1.18")
NOTES:
• Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above
and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D3
133.35 (5.25)
128.95 (5.076)
2x 3.00 (2x 0.118)
1.27 +/-0.1
(0.05+/-0.004)
4x 4.00+/-0.1
(4x 0.157+/-0.004)
2x DIA. 2.50 +0.1/-0.00
(2x DIA 0.098 + 0.004/-0.00)
1
www.DataSheet4U.6c.3o5 m
(0.25)
2.175 (0.085)
3.80 (0.149)
64.77 (2.55)
6.35 (0.25)
4.175 (0.164)
1.0 ±0.05
(0.039 ±0.002)
92
1.80 (0.070)
49.53 (1.95)
1.27
(0.05)
0.20 ±0.15
(0.008 ±0.006)
2.50 (0.098)
3.99 MAX
(0.157 MAX)
120.65 (4.75)
93 184
March 2005
Rev. 0
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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