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PDF FAN6754 Data sheet ( Hoja de datos )

Número de pieza FAN6754
Descripción Highly Integrated Green-Mode PWM Controller
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FAN6754 Hoja de datos, Descripción, Manual

September 2009
FAN6754
Highly Integrated Green-Mode PWM Controller
Brownout and Constant Power Limited by HV Pin
Features
ƒ High-Voltage Startup
ƒ AC Input Brownout Protection with Hysteresis
ƒ Low Operating Current: 1.7mA
ƒ Linearly Decreasing PWM Frequency to 22KHz
ƒ Frequency Hopping to Reduce EMI Emission
ƒ Fixed PWM Frequency: 65KHz
ƒ Peak-Current-Mode Control
ƒ Cycle-by-Cycle Current Limiting
ƒ Leading-Edge Blanking (LEB)
ƒ Internal Open-Loop Protection
ƒ GATE Output Maximum Voltage Clamp: 13V
ƒ VDD Under-Voltage Lockout (UVLO)
ƒ VDD Over-Voltage Protection (OVP)
ƒ Programmable Over-Temperature Protection (OTP)
ƒ Internal Latch Circuit (OVP, OTP)
ƒ Open-Loop Protection (OLP); Restart for MR, Latch
for ML
www.DataShƒeet4BUu.cioltm-in 8ms Soft-Start Function
ƒ Constant Power Limit (Full AC Input Range)
ƒ Internal OTP Sensor with Hysteresis
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
ƒ Power Adapters
Description
The highly integrated FAN6754 PWM controller
provides several features to enhance the performance
of flyback converters. To minimize standby power
consumption, a proprietary green-mode function
provides off-time modulation to continuously decrease
the switching frequency under light-load conditions.
Under zero-load and very light-load conditions,
FAN6754 saves PWM pulses by entering deep burst
mode. This burst mode function enables the power
supply to meet international power conservation
requirements.
FAN6754 integrates a frequency-hopping function
internally to reduce EMI emission of a power supply
with minimum line filters. Built-in synchronized slope
compensation is accomplished by, proprietary internal
compensation for constant output power limit over
universal AC input range. Also, the gate output is
clamped at 13V to protect the external MOSFET from
over-voltage damage.
Other protection functions include AC input brownout
protection with hysteresis and VDD over-voltage
protection. For over-temperature protection, an external
NTC thermistor can be applied to sense the external
switcher’s temperature. When VDD OVP or OTP are
activated, an internal latch circuit is used to latch-off the
controller. The latch mode is reset when the VDD supply
is removed.
FAN6754 is available in an 8-pin SOP package.
Ordering Information
Part Number
Operating
Temperature Range
FAN6754MRMY
FAN6754MLMY
-40 to +105°C
-40 to +105°C
Eco
Status
RoHS
RoHS
Package
8-Pin, Small Outline Package (SOP)
8-Pin, Small Outline Package (SOP)
Packing Method
Tape & Reel
Tape & Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FAN6754 • Rev. 1.0.0
www.fairchildsemi.com

1 page




FAN6754 pdf
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
VDD Section
VOP
VDD-ON
VDD-OFF
VDD-OLP
VDD-LH
Continuously Operating Voltage
Start Threshold Voltage
Minimum Operating Voltage
IDD-OLP Off Voltage
Threshold Voltage on VDD Pin for
Latch-Off Release Voltage
VDD-AC
Threshold Voltage on VDD Pin for
Disable AC recovery to avoid
Startup Failed
IDD-ST
IDD-OP1
Startup Current
Operating Supply Current when
PWM operation
VDD-ON – 0.16V
VDD=20V, FB=3V Gate
Open
IDD-OP2
Operating Supply Current when
Gate Stop
VDD=20V, FB=3V
Operating Current at PWM-Off
ILH Phase Under Latch-Off
Conduction
VDD=5V
IDD-OLP
Internal Sink Current under Latch-
Off Conduction
VDD-OLP+0.1V
VDD-OVP
tD-VDDOVP
VDD Over-Voltage Protection
VDD Over-Voltage Protection
Debounce Time
HV Section
IHV Supply Current from HV Pin
www.DataSheVeAt4CU-O.FcFom Brownout Threshold
VAC-ON Brownin Threshold(Eq.2)
VAC VAC-ON - VAC-OFF
tS-CYCLE Line Voltage Sample Cycle
VAC=90V(VDC=120V),
VDD=0V
DC Source Series
R=200kto HV Pin
See Equation 1
DC Source Series
R=200kto HV Pin
See Equation 2
DC Source Series
R=200kto HV Pin
FB > VFB-N
FB < VFB-G
tH-TIME Line Voltage Hold Period
tD-AC-OFF PWM Turn-off Debounce Time
FB > VFB-N
FB < VFB-G
Min. Typ. Max. Units
24
15.5 16.5 17.5
8 9 10
5.5 6.5 7.5
3.5 4.0 4.5
VDD-OFF
+2.5
VDD-OFF
+3.0
1.7
VDD-OFF
+3.5
30
2.0
1.2 1.5
V
V
V
V
V
V
µA
mA
mA
30 60 90 µA
180 210 240
24 25 26
75 165 255
µA
V
µs
1.50 2.75 4.00
92 102 112
mA
V
104 114 124
V
6 12 18 V
220
μs
650
20 μs
65 75 85 ms
180 235 290 ms
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FAN6754 • Rev. 1.0.0
5
www.fairchildsemi.com

5 Page





FAN6754 arduino
Functional Description
Startup Current
For startup, the HV pin is connected to the line input
through an external diode and resistor; RHV, (1N4007 /
150Krecommended). Peak startup current drawn
from the HV pin is (VAC× 2 ) / RHV and charges the
hold-up capacitor through the diode and resistor. When
the VDD capacitor level reaches VDD-ON, the startup
current switches off. At this moment, the VDD capacitor
only supplies the FAN6754 to keep the VDD until the
auxiliary winding of the main transformer provides the
operating current.
Operating Current
Operating current is around 1.7mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to reduce the switching frequency in light-
load and no-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference.
Once VFB is lower than the threshold voltage (VFB-N),
switching frequency is continuously decreased to the
minimum green-mode frequency of around 22KHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current-sense signal and VFB, the feedback voltage.
When the voltage on the SENSE pin reaches around
VCOMP = (VFB–0.6)/4, the switch cycle is terminated
immediately. VCOMP is internally clamped to a variable
www.DataShveoeltta4Uge.coamround 0.46V for low-line output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 9V, respectively. During startup, the hold-
up capacitor must be charged to 16.5V through the
startup resistor to enable the IC. The hold-up capacitor
continues to supply VDD until the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 9V during startup. This UVLO
hysteresis window ensures that hold-up capacitor is
adequate to supply VDD during startup.
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
13V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 8ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
FAN6754 inserts a synchronized, positive-going, ramp
at every switching cycle.
Constant Output Power Limit
When the SENSE voltage across sense resistor RSENSE
reaches the threshold voltage, around 0.46V for low-line
condition, the output GATE drive is turned off after a
small delay, tPD. This delay introduces an additional
current proportional to tPD • VIN / LP. Since the delay is
nearly constant regardless of the input voltage VIN,
higher input voltage results in a larger additional current
and the output power limit is higher than under low input
line voltage. To compensate this variation for a wide AC
input range, a power-limiter is controlled by the HV pin
to solve the unequal power-limit problem. The power
limiter is fed to the inverting input of the current limiting
comparator. This results in a lower current limit at high-
line inputs than at low-line inputs.
Brownout and Constant Power Limited by
HV Pin
Unlike previous PWM controllers, FAN6754’s HV pin
can also detect the AC line voltage brownout function
and set the current limit level. Using a fast diode and
startup resistor to sample the AC line voltage, the peak
value refreshes and is stored in a register at each
sampling cycle. When internal update time is met, this
peak value is used for brownout and current-limit level
judgment. Equation 1 and 2 calculate the level of
brownin or brownout converted to RMS value. For
power saving, FAN6754 enlarges the sampling cycle to
lower the power loss from HV sampling at light load
condition.
VAC-ON (RMS)
=( 0.9V
×
(RHV +1.6) ) /
1.6
2
(1)
VAC-OFF (RMS)=(
0.81V
×
(RHV +1.6) )
1.6
/
2
; the unit of RHV is kΩ
(2)
© 2009 Fairchild Semiconductor Corporation
FAN6754 • Rev. 1.0.0
11
www.fairchildsemi.com

11 Page







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