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PDF XRT91L34 Data sheet ( Hoja de datos )

Número de pieza XRT91L34
Descripción QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
Fabricantes Exar Corporation 
Logotipo Exar Corporation Logotipo



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XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
OCTOBER 2007
REV. 1.0.1
GENERAL DESCRIPTION
The XRT91L34 is a fully integrated quad channel
multirate Clock and Data Recovery (CDR) device for
SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52
Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0
applications. The device provides Clock and Data
Recovery (CDR) function by synchronizing its on-chip
Voltage Controlled Oscillator (VCO) to the incoming
serial data stream. The device internally monitors
Loss of Lock (LOL) conditions and automatically
mutes recovered data upon Loss of Signal (LOS)
conditions.
CLOCK AND DATA RECOVERY OVERVIEW
The clock and data recovery (CDR) unit accepts the
high speed NRZ serial data from the LVDS or
Differential LVPECL receiver and generates a clock
that is the same frequency as the incoming data. The
CDR block uses a reference clock to train and
monitor its clock recovery PLL. All four channels
share a single 77.76MHz or 19.44MHz reference
clock. Upon startup, the PLL locks to the local
reference clock. Once this is achieved, the PLL
FIGURE 1. BLOCK DIAGRAM OF XRT91L34
attempts to lock onto the incoming receive serial data
stream. Whenever the recovered clock frequency
deviates from the local reference clock frequency by
more than approximately ±500 ppm, the clock
recovery PLL will switch and lock back onto the local
reference clock and declare a Loss of Lock.
Whenever a Loss of Lock or a Loss of Signal event
occurs, the CDR will continue to supply a recovered
clock (based on the local reference) to the framer/
mapper device. When the SDEXT is de-asserted by
the optical module or when internal DLOS is
asserted, the receive serial data output will be forced
to a logic zero state for the entire duration that a LOS
condition is declared. This acts as a receive data
mute upon LOS function to prevent random noise
from being misinterpreted as valid incoming data.
When the SDEXT becomes active and the recovered
clock is determined to be within ±500 ppm accuracy
with respect to the local reference source and LOS is
no longer declared, the clock recovery PLL will switch
and lock back onto the incoming receive serial data
stream. Figure 1 shows the block diagram of the
XRT91L34.
RESET
HOST /HW
DLOSDIS /SDI
0
1
INT
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CS
SCLK
SDO
DLOSDIS
SDI
Serial Proccesor
Interface
RXDI0P
RXDI0N
LVDS/LVPECL
Input Drivers
100
RXDATAIN
RX LOOP
FILTER
XRT91L34
Global Control Block
CDR
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
CDRDIS0
DATA0RATE1
DATA0RATE0
SDEXT0
POL0
Channel Control Block
DLOSDIS
DLOS
REFCLKP
REFCLKN
TEST
OUTCFG
CDRREFSEL
19.44 / 77.76 MHz
TTLREFCLK
LVDS/LVPECL LEVEL SELECT
RCLKDIS0
LVDS/LVPECL
Output Drivers
RECVD-
DATAOUT 0
1
RECVD-
CLKOUT
0
1
HOST MODE
ONLY
RXDO0P
RXDO0N
RXCLKO0P
RXCLKO0N
LOL0
Channel 0
Channel 1
Channel 2
Channel 3
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




XRT91L34 pdf
XRT91L34
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
5.0 REGISTER MAP AND BIT DESCRIPTIONS ....................................................................................... 26
TABLE 8: MICROPROCESSOR INTERFACE REGISTER MAP ................................................................................................................ 26
TABLE 9: MICROPROCESSOR INTERFACE REGISTER 0X00 BIT DESCRIPTION .................................................................................... 27
TABLE 10: MICROPROCESSOR INTERFACE REGISTER 0X01 BIT DESCRIPTION .................................................................................. 28
TABLE 11: MICROPROCESSOR INTERFACE REGISTER 0X02 BIT DESCRIPTION .................................................................................. 28
TABLE 12: MICROPROCESSOR INTERFACE REGISTER 0X03 BIT DESCRIPTION .................................................................................. 29
TABLE 13: MICROPROCESSOR INTERFACE REGISTER 0X04 BIT DESCRIPTION .................................................................................. 29
TABLE 14: MICROPROCESSOR INTERFACE REGISTER 0X05 BIT DESCRIPTION .................................................................................. 29
TABLE 15: MICROPROCESSOR INTERFACE REGISTER 0X08, 0X10, 0X18, 0X20 BIT DESCRIPTION .................................................... 30
TABLE 16: MICROPROCESSOR INTERFACE REGISTER 0X09, 0X11, 0X19, 0X21 BIT DESCRIPTION .................................................... 31
TABLE 17: MICROPROCESSOR INTERFACE REGISTER 0X0A, 0X12, 0X1A, 0X22 BIT DESCRIPTION ................................................... 32
6.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 33
ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 33
TABLE 18: ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS ........................................................................................... 33
TABLE 19: POWER AND CURRENT DC ELECTRICAL CHARACTERISTICS ............................................................................................ 33
TABLE 20: LVDS/DIFFERENTIAL LVPECL INPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS................................................ 34
FIGURE 19. LVDS/DIFFERENTIAL LVPECL VOLTAGE PARAMETER CONVENTION ............................................................................. 35
TABLE 21: LVDS OUTPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS ................................................................................. 36
TABLE 22: DIFFERENTIAL LVPECL OUTPUT LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS....................................................... 36
TABLE 23: LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS ....................................................................................... 36
TABLE 24: ORDERING INFORMATION............................................................................................................................................... 37
PACKAGE DIMENSIONS ................................................................................................ 37
TABLE 25: REVISION HISTORY........................................................................................................................................................ 38
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XRT91L34 arduino
REV. 1.0.1
XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
SERIAL MICROPROCESSOR INTERFACE
NAME
HOST/HW
LEVEL
LVTTL,
LVCMOS
TYPE
I
CS
LVTTL,
I
LVCMOS
SCLK
LVTTL,
LVCMOS
I
DLOSDIS
/SDI
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LVTTL,
LVCMOS
I
PIN DESCRIPTION
122 Host or Hardware Mode Select Input
The XRT91L34 offers two modes of operation for interfacing to the
device. The Host mode uses a serial microprocessor interface for
programming individual registers. The Hardware mode is controlled
by the state of the hardware pins set by the user. When left uncon-
nected, by default, the device is configured in the Hardware mode.
"Low" = Hardware Mode
"High" = Host Mode
This pin is provided with an internal pull-down.
38 Chip Select Input (Host Mode)
Active "Low" signal. This signal enables the serial microprocessor
interface by pulling chip select "Low". The serial microprocessor is
disabled when the chip select signal returns "High".
NOTES:
1. The serial microprocessor interface does not support burst
mode. Chip Select must be de-asserted after each
operation cycle.
2. Chip Select is only active in Host Mode.
This pin is provided with an internal pull-up.
37 Serial Clock Input (Host Mode Only)
Once CS is pulled "Low", the serial microprocessor interface
requires 16 clock cycles for a complete Read or Write operation.
Serial Clock Input is only active in Host Mode.
This pin is provided with an internal pull-down.
39 Serial Data Input (Host Mode Only)
When CS is pulled "Low", the serial data input is sampled on the ris-
ing edge of SCLK.
Serial Data Input is only active in Host Mode.
This pin is provided with an internal pull-down.
SDO
INT
LVCMOS
O
LVCMOS
O
Hardware Mode This pin is functions as the DLOSDIS control pin.
40 Serial Data Output (Host Mode Only)
If a Read function is initiated, the serial data output is updated on
the falling edge of SCLK8 through SCLK15, with the LSB (D0)
updated first. This enables the data to be sampled on the rising
edge of SCLK9 through SCLK16.
Serial Data Output is only active in Host Mode.
41 Interrupt Output (Host Mode Only)
Active "Low" signal. This signal is asserted "Low" when a change in
alarm status occurs. Once the status registers have been read, the
interrupt pin will return "High".
Interrupt Output is only active in Host Mode.
NOTE: This open-drain output pin requires an external pull-up
resistor.
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