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PDF P89LPC952 Data sheet ( Hoja de datos )

Número de pieza P89LPC952
Descripción (P89LPC952 / P89LPC954) 8-bit microcontroller
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! P89LPC952 Hoja de datos, Descripción, Manual

P89LPC952/954
8-bit microcontroller with accelerated two-clock 80C51 core
8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC
Rev. 04 — 24 July 2008
Product data sheet
1. General description
The P89LPC952/954 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC952/954 in order to reduce component count,
board space, and system cost.
2. Features
2.1 Principal features
I 8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
I 256-byte RAM data memory and a 256-byte auxiliary on-chip RAM.
I 8-input multiplexed 10-bit ADC with window comparator that can generate an interrupt
for in or out of range results. Two analog comparators with selectable inputs and
reference source.
I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as a RTC.
I Two enhanced UARTs with a fractional baud rate generator, break detect, framing
error detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
I High-accuracy internal RC oscillator option, with clock doubler option, allows operation
without external oscillator components. The RC oscillator option is selectable and fine
tunable. Fast switching between the internal RC oscillator and any oscillator source
provides optimal support of minimal power active mode with fast switching to
maximum performance.
I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
I 44-pin and 48-pin packages with 40 and 42 I/O pins minimum while using on-chip
oscillator and reset options.
I Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins
have high sinking capability (20 mA). A maximum limit is specified for the entire chip.
I Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
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P89LPC952 pdf
NXP Semiconductors
5. Functional diagram
P89LPC952/954
8-bit microcontroller with 10-bit ADC
AD05
AD00
AD01
AD02
AD03
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CLKOUT
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
XTAL1
PORT 0
PORT 3
PORT 5
(1) 48-pin package.
Fig 2. Functional diagram
VDD VSS
P89LPC952
P89LPC954
PORT 1
PORT 2
(1)
(1)
TXD0
RXD0
T0
INT0
INT1
RST
SCL
SDA
AD04
AD07
AD06
MOSI
MISO
SS
SPICLK
002aab358
PORT 4
TRIG
TXD1
RXD1
TDI
TCLK
www.DataSheet4U.com
P89LPC952_954_4
Product data sheet
Rev. 04 — 24 July 2008
© NXP B.V. 2008. All rights reserved.
5 of 69

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P89LPC952 arduino
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
Table 3. Pin description …continued
Symbol
Pin
LQFP48 PLCC44
P1.5/RST
47
5
P1.6
P1.7/AD04
46
43
P2.0 to P2.5
4
2
P2.0/AD07
P2.1/AD06
P2.2/MOSI
42
41
30
1
44
34
P2.3/MISO
29
P2.4/SS
28
33
32
LQFP44
43
42
40
39
38
28
27
26
Type Description
I P1.5 — Port 1 bit 5 (input only).
I RST — External Reset input during power-on or maybe a
reset input/output if selected via UCFG1 and UCFG2. When
functioning as a reset input or input/output, a LOW on this
pin resets the microcontroller, causing I/O ports and
peripherals to take on their default states, and the processor
begins execution at address 0. When functioning as a reset
output or input/output an internal reset source will drive this
pin LOW. Also used during a power-on sequence to force
ISP mode. When using an oscillator frequency above
12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the
device in reset at power-up until VDD has reached its
specified level. When system power is removed VDD will
fall below the minimum specified operating voltage.
When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit
may be required to hold the device in reset when VDD
falls below the minimum specified operating voltage.
I/O P1.6 — Port 1 bit 6.
I/O P1.7 — Port 1 bit 7.
I AD04 — ADC0 channel 4 analog input.
I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable
output type. During reset Port 2 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 2 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to Section 7.13.1 “Port configurations”
and Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described
below:
I/O P2.0 — Port 2 bit 0.
I AD07 — ADC0 channel 7 analog input.
I/O P2.1 — Port 2 bit 1.
I AD06 — ADC0 channel 6 analog input.
I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as
master, this pin is output; when configured as slave, this pin
is input.
I/O P2.3 — Port 2 bit 3.
I/O MISO — When configured as master, this pin is input, when
configured as slave, this pin is output.
I/O P2.4 — Port 2 bit 4.
I/O SS — SPI Slave select.
www.DataSheet4U.com
P89LPC952_954_4
Product data sheet
Rev. 04 — 24 July 2008
© NXP B.V. 2008. All rights reserved.
11 of 69

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