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PDF VP77 Data sheet ( Hoja de datos )
| Número de pieza | VP77 | |
| Descripción | Video Drcoder | |
| Fabricantes | ETC | |
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VP77
Video Decoder for Portable LCD Display
(Preliminary)
Version: 0.96
Date : Apr. 7, 2005
www.DataSheet4U.com
Confidential
VP77 Data Sheet
1 page  
Video Decoder for Portable LCD Display
VP77 (Ver. 0.96)
4. Pin Assignment
PIN NAME
COMP_Y
Y
CVBS1
RAIN
RMIDBYPASS
PIN TYPE
A
A
A
A
A
CB
C
CVBS2
GAIN
GMIDBYPASS
A
A
A
A
A
PIN#
13
14
15
16
18
20
21
22
23
26
CR
BAIN
BMIDBYPASS
A
A
A
28
29
30
SOGIN
REFBYPASS
FILT
DHS
DVS
VOUT
TPAD
A
A
A
I(SMT, PD)
I(SMT, PD)
A
A
24
31
34
127
126
12
35
C_VS/OVR
IO(PD4)
44
C_HS/OVG
IO(PD4)
45
C_FID/OVB
IO(PD4)
43
C_CLK/OVCLK IO(PD4)
46
C_D[7:4],
C_D3/OVS,
C_D2/OHS,
C_D1/OVI,
C_D0/OVFB
IO(PD4)
54~51,
50,
49,
48,
47
SDA
SCL
IICADRSEL
TESTA
TESTS
XTAL1
XTAL2
RSTN
PWM1
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IO(SMT, PU4) 4
IO(SMT, PU4) 3
I(PD)
8
I(PD)
I(PD)
39
40
I
O
I(SMT)
66
65
5
O(PD4)
O(PD4)
77
78
Confidential
DESCRIPTION
Y of Component video
Luma of S-Video Input
Composite video input 1
Red Channel Analog Input
R channel internal midscale voltage bypass
(default to be ground)
CB of Component video
Chroma of S-Video Input
Composite video input 2
Green Channel Analog Input
G channel internal midscale voltage bypass
(default to be ground)
CR of Component video
Blue Channel Analog Input
B channel internal midscale voltage bypass
(default to be ground)
Sync-on-Green slicer input
Internal reference bypass
External filter connection for PLL
VGA input H sync
VGA input V sync
Buffered composite video output
Test mode output
Vertical sync of video port /
Overlay color select R input of external OSD
Horizontal sync of video port /
Overlay color select G input of external OSD
Field ID/
Overlay color select B input of external OSD
Clock for video port/
Overlay clock of external OSD
YUV data of video port bit 7~0/
YUV bit-3 alternative to Overlay VSYNC of ext-OSD/
YUV bit-2 alternative to Overlay HSYNC of ext-OSD/
YUV bit-1 alternative to Overlay intensity of ext- OSD/
YUV bit-0alternative to Overlay fast blanking of
ext-OSD
Serial I/F data in/out
Serial I/F clock
Serial I/F sub-address setting
Test pin A
Test pin S
Input external free-run clock of 20 MHz
Output external free-run clock of 20 MHz
Reset signal (active low)
PWM output 1
PWM output 2
5
5 Page 
Video Decoder for Portable LCD Display
VP77 (Ver. 0.96)
Bit ACCESS
[7:4] R/W
[3:0] R/W
SYMBOL
PLLDIV[3:0]
RESERVED
Description
This register is used for bits 3-0 of PLL divider. The PLL divider
has total of 12 bits value (default at 1693).
(PLLDIV[3:0] is default to 0DH)
02H Red Gain Control Register
Bit ACCESS
[7:0] R/W
SYMBOL
RGAIN
Description
This register controls the Red color ADC input range (i.e.
Contrast). Smaller values give more contrast.
(deafult to 80H)
03H Green Gain Control Register
Bit ACCESS
[7:0] R/W
SYMBOL
GGAIN
Description
This register controls the Green color ADC input range (i.e.
Contrast). Smaller values give more contrast. (deafult to 80H)
04H Blue Gain Control Register
Bit ACCESS
[7:0] R/W
SYMBOL
BGAIN
Description
This register controls the Blue color ADC input range (i.e.
Contrast). Smaller values give more contrast. (deafult to 80H)
05H Red offset Control Register
Bit ACCESS
[7:1] R/W
[0] R/W
SYMBOL
ROFF
RESERVED
Description
This register controls the Red color DC offset (i.e. Brightness).
Smaller values give a brighter image (default to 1000000b)
06H Green offset Control Register
Bit ACCESS
[7:1] R/W
[0] R/W
SYMBOL
GOFF
RESERVED
Description
This register controls the Green color DC offset (i.e.
Brightness). Smaller values give a brighter image.
(default to 1000000b)
07H Blue offset Control Register
Bit ACCESS
[7:1] R/W
[0] R/W
SYMBOL
BOFF
RESERVED
Description
This register controls the Blue color DC offset (i.e. Brightness).
Smaller values give a brighter image. (default to 1000000b)
08H Clamp Placement Register
Bit ACCESS
SYMBOL
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Description
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11
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| PDF Descargar | [ Datasheet VP77.PDF ] | |
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