PDF 17C158CV Data sheet ( Hoja de datos )

Número de pieza	17C158CV
Descripción	XR17C158CV
Fabricantes	Exar Corporation
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No Preview Available ! xr www.DataSheet4U.com AUGUST 2005 GENERAL DESCRIPTION The XR17C1581 (158) is an octal Universal Asynchronous Receiver and Transmitter (UART). The device is designed to meet the 32-bit PCI Bus and high bandwidth requirement in communication systems. The global interrupt source register provides a complete interrupt status indication for all 8 channels to speed up interrupt parsing. Each UART has its own 16C550 compatible set of configuration registers, transmit and receive FIFOs of 64 bytes, fully programmable transmit and receive FIFO level triggers, transmit and receive FIFO level counters, automatic RTS/CTS or DTR/DSR hardware flow control with programmable hysteresis, automatic software (Xon/Xoff) flow control, IrDA (Infrared Data Association) encoder/decoder, 8 multi-purpose definable inputs/outputs, and a 16-bit general purpose timer/counter. NOTE: 1 Covered by U.S. Patents #5,649,122 and #5,949,787 APPLICATIONS • Remote Access Servers • Ethernet Network to Serial Ports • Network Management • Factory Automation and Process Control • Point-of-Sale Systems • Multi-port RS-232/RS-422/RS-485 Cards FIGURE 1. BLOCK DIAGRAM XR17C158 5V PCI BUS OCTAL UART FEATURES REV. 1.4.3 • High Performance Octal UART • 32-bit PCI Bus Interface with EEPROM Interface • Interrupt Source Register for all 8 UARTs • Data Transfer in Byte, Word and Double-word • Read/Write Burst Operation • Each UART Includes • 16C550 Compatible Registers • 64-byte Transmit and Receive FIFOs • Transmit and Receive FIFO Level Counters • Automatic RTS/CTS or DTR/DSR Flow Control • Automatic Xon/Xoff Software Flow Control • RS485 Half-duplex Control with Selectable Delay • Infrared (IrDA 1.0) Data Encoder/Decoder • Programmable Data Rate with Prescaler • Up to 6.25 Mbps Serial Data Rate • Eight Multi-Purpose Inputs/outputs • A General Purpose 16-bit Timer/Counter • Sleep Mode with Automatic Wake-up • 5V Operation (PCI Compliance) • Same package and pinout as the XR17C154, XR17D154 and XR17D158 • 144-pin LQFP Package (20x20x1.4mm) CLK RST# AD[31:0] C/BE[3:0]# FRAME# IRDY# TRDY# DEVSEL# STOP# INTA# IDSEL PERR# SERR# PAR EECK EEDI EEDO EECS PCI Local Bus Interface Device Configuration Registers Configuration Space Registers EEPROM Interface 16-bit Timer/Counter UART Channel 0 UART Regs BRG 64 Byte TX FIFO TX & RX IR ENDEC 64 Byte RX FIFO UART Channel 1 UART Channel 2 UART Channel 3 UART Channel 4 UART Channel 5 UART Channel 6 UART Channel 7 Multi-pur.pose Inputs/Outputs Crystal Osc/Buffer TX0, RX0, DTR0#, DSR0#, RTS0#, CTS0#, CD0#, RI0# TX7, RX7, DTR7#, DSR7#, RTS7#, CTS7#, CD7#, RI7# MPIO0- MPIO7 XTAL1 XTAL2 TMRCK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page xr www.DataShReEeVt4.U1..c4o.3m Pin Description NAME TX6 RX6 PIN # 62 55 RTS6# CTS6# DTR6# DSR6# CD6# RI6# TX7 RX7 60 56 61 57 58 59 54 47 RTS7# 52 CTS7# 48 DTR7# 53 DSR7# 49 CD7# 50 RI7# 51 ANCILLARY SIGNALS MPIO0 108 MPIO1 107 MPIO2 74 MPIO3 73 MPIO4 68 MPIO5 67 MPIO6 66 MPIO7 65 EECK 116 XR17C158 5V PCI BUS OCTAL UART TYPE O I O I O I I I O I O I O I I I DESCRIPTION UART channel 6 Transmit Data or infrared transmit data. UART channel 6 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses typically idle LOW but can be inverted inter- nally prior the decoder by FCTR[4]. UART channel 6 Request to Send or general purpose output (active low). UART channel 6 Clear to Send or general purpose input (active low). UART channel 6 Data Terminal Ready or general purpose output (active low). UART channel 6 Data Set Ready or general purpose input (active low). UART channel 6 Carrier Detect or general purpose input (active low). UART channel 6 Ring Indicator or general purpose input (active low). UART channel 7 Transmit Data or infrared transmit data. UART channel 7 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses typically idle LOW but can be inverted inter- nally prior the decoder by FCTR[4]. UART channel 7 Request to Send or general purpose output (active low). UART channel 7 Clear to Send or general purpose input (active low). UART channel 7 Data Terminal Ready or general purpose output (active low). UART channel 7 Data Set Ready or general purpose input (active low). UART channel 7 Carrier Detect or general purpose input (active low). UART channel 7 Ring Indicator or general purpose input (active low). I/O Multi-purpose input/output 0. The function of this pin is defined thru the Con- figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT I/O Multi-purpose input/output 1. The function of this pin is defined thru the Con- figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. I/O Multi-purpose input/output 2. The function of this pin is defined thru the Con- figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. I/O Multi-purpose input/output 3. The function of this pin is defined thru the Con- figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. I/O Multi-purpose input/output 4. The function of this pin is defined thru the Con- figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. I/O Multi-purpose input/output 5. The function of this pin is defined thru the Con- figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. I/O Multi-purpose input/output 6. The function of this pin is defined thru the Con- figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. I/O Multi-purpose input/output 7. The function of this pin is defined thru the Con- figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. O Serial clock to EEPROM. An internal clock of CLK divide by 256 is used for reading the vendor and sub-vendor ID during power up or reset. However, it can be manually clocked thru the Configuration Register REGB. 5 5 Page xr www.DataShReEeVt4.U1..c4o.3m XR17C158 5V PCI BUS OCTAL UART TABLE 2: XR17C158 DEVICE CONFIGURATION REGISTERS OFFSET ADDRESS MEMORY SPACE 0x000 - 0x00F UART channel 0 Regs READ/WRITE (Table 11 & Table 12) DATA WIDTH COMMENT 8/16/24/32 First 8 regs are 16550 compatible 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIG. REGISTERS (Table 3) 8/16/24/32 0x094 - 0x0FF Reserved 0x100 - 0x13F UART 0 – Read FIFO Read-Only 8/16/24/32 64 bytes of RX FIFO data 0x100 - 0x13F UART 0 – Write FIFO Write-Only 8/16/24/32 64 bytes of TX FIFO data 0x140 - 0x17F Reserved 0x180 - 0x1FF UART 0 – Read FIFO with errors Read-Only 16/32 64 bytes of RX FIFO data + LSR 0x200 - 0x20F UART channel 1 Regs 0x210 - 0x2FF 0x300 - 0x33F 0x300 - 0x33F 0x340 - 0x37F 0x380 - 0x3FF Reserved UART 1 – Read FIFO UART 1 – Write FIFO Reserved UART 1 – Read FIFO with errors (Table 11 & Table 12) Read-Only Write-Only Read-Only 8/16//24/32 First 8 regs are 16550 compatible 8/16/24/32 64 bytes of RX FIFO data 8/16/24/32 64 bytes of TX FIFO data 16/32 64 bytes of RX FIFO data + LSR 0x400 - 0x40F UART channel 2 Regs 0x410 - 0x4FF 0x500 - 0x53F 0x500 - 0x53F 0x540 - 0x57F 0x580 - 0x5FF Reserved UART 2 – Read FIFO UART 2 – Write FIFO Reserved UART 2 – Read FIFO with errors (Table 11 & Table 12) Read-Only Write-Only Read-Only 8/16/24/32 First 8 regs are 16550 compatible 8/16/24/32 64 bytes of RX FIFO data 8/16/24/32 64 bytes of TX FIFO data 16/32 64 bytes of RX FIFO data + LSR 0x600 - 0x60F UART channel 3 Regs 0x610 - 0x6FF 0x700 - 0x73F 0x700 - 0x73F Reserved UART 3 – Read FIFO UART 3 – Write FIFO (Table 11 & Table 12) Read-Only Write-Only 8/16/24/32 First 8 regs are 16550 compatible 8/16/24/32 64 bytes of RX FIFO data 8/16/24/32 64 bytes of TX FIFO data 11 11 Page

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