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PDF M37220M3-xxxSP Data sheet ( Hoja de datos )
| Número de pieza | M37220M3-xxxSP | |
| Descripción | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
www.DataSheet4U.com
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
PIN DESCRIPTION
Pin Name
VCC, VSS
Power source
Input/
Output
Functions
Apply voltage of 5 V ± 10 % (typical) to VCC, and 0 V to VSS.
CNVSS
RESET
CNVSS
Reset input
Input
XIN
XOUT
Clock input
Clock output
Input
Output
P00/PWM0–
P05/PWM5,
P06/INT2/
A-D4,
P07/INT1
P10–P14,
P15/A-D1
INT3,
P16/A-D2,
P17/A-D3
P20/SCLK,
P21/SOUT,
P22/SIN,
P23/TIM3,
P24/TIM2,
P25–P27
P30/A-D5/
DA1,
P31/A-D6/
DA2,
P32
P33/OSC1,
P34/OSC2
I/O port P0
PWM output
External interrupt
input
Analog input
I/O port P1
Analog input
External interrupt
input
I/O port P2
External clock
input
Serial I/O data
input/output
Serial I/O synchro-
nizing clock input/
output
I/O port P3
Analog input
D-A conversion
output
Input port P3
Clock input for
CRT display
Clock output for
CRT display
I/O
Output
Input
Input
I/O
Input
Input
I/O
Input
I/O
I/O
I/O
Input
Output
Input
Input
Output
This is connected to VSS.
To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output. The note out of this Table gives a full of port P0 function.
Pins P00–P05 are also used as PWM output pins PWM0–PWM5 respectively.The output
structure is N-channel open-drain output.
Pins P06, P07 are also used as external interrupt input pins INT2, INT1 respectively.
Pins P06 is also used as an analog interrupt input pin A-D4.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P15–P17 are also used as an analog input pins A-D1 to A-D3.
Pin P15 is also used as an external interrupt input pins INT3.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P23, P24 is also used an external clock input pins TIM3, TIM2 respectively.
Pins P21, P22 are also used serial I/O data input/output pins SOUT, SIN respectively. The
output structure is N-channel open-drain output.
Pin P20 is also used serial I/O syncronizing clock input/output pin SCLK. The output struc-
ture is N-channel open-drain output.
Ports P30–P32 are a 3-bit I/O port and have basically the same functions as port P0. Either
CMOS output or N-channel open-drain output structure can be selected as the ports P30
and P31. The output structure of port P32 is N-channel open-drain output.
Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively.
Pins P30, P31 are also used as D-A conversion output pins DA1, DA2 respectively.
Ports P33, P34 are a 2-bit input port.
Pin P33 is also used as CRT display clock input pin OSC1.
Pin P34 is also used as CRT display clock output pin OSC2.The output structure is CMOS
output.
4
5 Page 
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
www.DataSheet4U.com
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts can be caused by 13 different sources consisting of 3 ex-
ternal, 9 internal, and 1 software sources. Interrupts are vectored
interrupts with priorities shown in Table 1. Reset is also included in
the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figure 5 shows the structure of
the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 6 shows interrupt control.
Interrupt Causes
(1) VSYNC and CRT interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The CRT interrupt occurs after character block display to the CRT
is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 5 of the interrupt input polarity register (address
00F916) : when this bit is “0,” a change from “L” to “H” is de-
tected; when it is “1,” a change from “H” to “L” is detected. Note
that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
(5) XIN/4096 interrupt
This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0
of the PWM output control register 1 to “0.”
(6) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Table 1. Interrupt vector addresses and priority
Interrupt source
Priority
Reset
CRT interrupt
1
2
INT2 interrupt
3
INT1 interrupt
Timer 4 interrupt
4
5
XIN/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
6
7
8
Timer 2 interrupt
Timer 1 interrupt
9
10
Serial I/O interrupt
11
INT3 interrupt
BRK instruction interrupt
12
13
Vector addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE516, FFE416
FFDF16, FFDE16
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable (software interrupt)
10
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