PDF M13S256328A Data sheet ( Hoja de datos )

Número de pieza	M13S256328A
Descripción	2M x 32 Bit x 4 Banks Double Data Rate SDRAM
Fabricantes	Elite Semiconductor Memory Technology
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No Preview Available ! ESMTwww.DataSheet4U.com DDR SDRAM Features M13S256328A 2M x 32 Bit x 4 Banks Double Data Rate SDRAM z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 2; 2.5; 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8, full page z Full page burst length for sequential burst type only z Start address of the full page burst should be even z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS) z DQS is edge-aligned with data for reads; center-aligned with data for WRITE z Data mask (DM) for write masking only z VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.7V z Auto & Self refresh z 64ms refresh period (8K cycle) z SSTL-2 I/O interface z 144Ball FBGA package Operating Frequencies : PRODUCT NO. M13S256328A -5BG MAX FREQ 200MHz VDD 2.5V PACKAGE COMMENTS 144 Ball FBGA Pb-free Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.2 1/47 1 page ESMT www.DataSheet4U.com M13S256328A DC Specifications Parameter Symbol Test Condition Operation Current (One Bank Active) Operation Current (One Bank Active) Precharge Power-down Standby Current IDD0 IDD1 tRC = tRC (min) tCK = tCK (min) Active – Precharge Burst Length = 2 tRC = tRC (min), CL= 2.5 IOUT = 0mA, Active-Read- Precharge IDD2P CKE ≤ VIL(max), tCK = tCK (min), All banks idle Idle Standby Current Active Power-down Standby Current Active Standby Current Operation Current (Read) Operation Current (Write) Auto Refresh Current Self Refresh Current IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = tCK (min) IDD3P All banks ACT, CKE ≤ VIL(max), tCK = tCK (min) One bank; Active-Precharge, tRC IDD3N = tRAS(max), tCK = tCK (min) IDD4R Burst Length = 2, CL= 2.5 , tCK = tCK (min), IOUT = 0Ma IDD4W Burst Length = 2, CL= 2.5 , tCK = tCK (min) IDD5 tRC ≥ tRFC(min) IDD6 CKE ≤ 0.2V Note 1. Enable on-chip refresh and address counters. AC Operation Conditions & Timing Specification Version -5 190 230 40 150 50 180 495 450 350 8 Unit Note -- mA - mA - mA - mA - mA - mA - mA - mA - mA - mA 1 AC Operation Conditions Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Different Voltage, CLK and CLK inputs Symbol VIH(AC) VIL(AC) VID(AC) Min VREF + 0.35 - 0.7 Max - VREF - 0.35 VDDQ+0.6 Unit V V V Note - - 1 Input Crossing Point Voltage, CLK and CLK inputs VIX(AC) 0.5VDDQ-0.2 0.5VDDQ+0.2 V 2 Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK . 2. The value of VIX is expected to equal 0.5VDDQ of the transmitting device and must track variations in the DC level of the same. Input / Output Capacitance (VDD = 2.3V~2.7V, VDDQ =2.3V~2.7V, TA = 25 °C , f = 1MHz) Parameter Input capacitance(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) Input capacitance (CLK, CLK ) Data & DQS input/output capacitance Input capacitance (DM) Symbol CIN1 CIN2 COUT CIN3 Min 1 1 1 1 Max 4 5 6.5 6.5 Unit pF pF pF pF Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.2 5/47 5 Page ESMT www.DataSheet4U.com M13S256328A Burst Length 2 4 8 Burst Address Ordering for Burst Length Starting Address (A2, A1,A0) Sequential Mode Interleave Mode xx0 0, 1 0, 1 xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S256328A also support a weak drive strength option, intended for lighter load and/or point-to-point environments. Mode Register Set CLK CLK 0 1 234 5678 COMMAND Prech arg e All Banks 1 Mode Register Set An y Com m an d tCK t 2 RP 1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.2 11/47 11 Page

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