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PDF M13S128324A Data sheet ( Hoja de datos )
| Número de pieza | M13S128324A | |
| Descripción | 1M x 32 Bit x 4 Banks Double Data Rate SDRAM | |
| Fabricantes | Elite Semiconductor Memory Technology | |
| Logotipo |  |
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Revision History
Revision 0.1 (May. 13 2005)
-Original
Revision 0.2 (Aug. 08 2005)
-Delete Non-Pb-free of ordering information
-Modify typing error of Pin Arrangement
Revision 1.0 (Mar. 08 2006)
-Delete “Preliminary” at every page
-Modify tWR from 2clk to 15ns
-Modify tWTR from 1clk to 2ns
Revision 1.1 (Oct. 25 2006)
-Add -4BG spec (only for CL4)
Revision 1.2 (Nov. 16 2006)
-Add 100 pin LQFP package
Revision 1.3 (Mar. 02 2007)
-Delete BGA ball name of packing dimensions
Revision 1.4 (Mar. 12 2007)
-Add -3.6 speed grade
Revision 1.5 (Mar. 21 2007)
-Add -4(CL3) specification
Revision 1.6 (Mar. 29 2007)
- Modify A10 to A8 on P26
- Modify the figure on P37
Revision 1.7 (Apr. 17 2007)
- Modify -4(CL3) VDD; VDDQ; spec
Revision 1.8 (May. 2 2007)
- Modify PD spec
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
1/49
1 page  
ESMT
www.DataSheet4U.com
Absolute Maximum Rating
M13S128324A
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD, VDDQ
VDDQ
TSTG
PD
IOS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
2
50
Unit
V
V
V
°C
W
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 °C )
Parameter
Symbol
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(VOUT =VDDQ-0.373V, min VREF, min VTT)
Output Low Current (Normal strength driver)
(VOUT = 0.373V)
Output High Current (Weak strength driver)
(VOUT =VDDQ-0.763V, min VREF, min VTT)
Output Low Current (Weak strength driver)
(VOUT = 0.763V)
VDD
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
II
IOZ
IOH
IOL
IOH
IOL
Min
-3.6 -4/5/6
2.5 2.375
2.5 2.375
0.49*VDDQ
VREF - 0.04
VREF + 0.15
-0.3
-5
-5
-16.8
+16.8
-9
+9
Max
-3.6 -4/5/6
2.7 2.625
2.7 2.625
0.51*VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
5
5
Unit
V
V
V
V
V
V
μA
μA
mA
Note
1
2
3
mA
mA
mA
Notes 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed 2% of the DC value.
2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF .
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
5/49
5 Page 
ESMT
www.DataSheet4U.com
Mode Register Definition
Mode Register Set (MRS)
M13S128324A
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the register is not defined, therefore the mode register must be written after
EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE
and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The
state of address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register.
Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The
mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3,
CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be
set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS
latencies.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
00
RFU
DLL TM
CAS Latency
BT
Burst Length
Mode Register
BA1 BA0
00
01
A8 DLL Reset
0 No
1 Yes
A7 Mode
0 Normal
1 Test
A3 Burst Type
0 Sequential
1 Interleave
Operating Mode
MRS Cycle
EMRS Cycle
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
Latency
Reserve
Reserve
2
3
4
Reserve
2.5
Reserve
Burst Length
A2 A1 A0
000
001
010
011
100
101
110
111
Latency
Sequential Interleave
Reserve Reserve
22
44
88
Reserve Reserve
Reserve Reserve
Reserve Reserve
Full Page Reserve
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
11/49
11 Page | ||
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| PDF Descargar | [ Datasheet M13S128324A.PDF ] | |
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