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PDF UPA1793 Data sheet ( Hoja de datos )
| Número de pieza | UPA1793 | |
| Descripción | SWITCHING N- AND P-CHANNEL POWER MOS FET | |
| Fabricantes | NEC | |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1793
SWITCHING
N- AND P-CHANNEL POWER MOS FET
DESCRIPTION
The µPA1793 is N- and P-Channel MOS Field Effect Transistors
designed for Motor Drive application.
FEATURES
• Low on-state resistance
N-Channel RDS(on)1 = 69 mΩ MAX. (VGS = 4.5 V, ID = 1.5 A)
RDS(on)2 = 72 mΩ MAX. (VGS = 4.0 V, ID = 1.5 A)
RDS(on)3 = 107 mΩ MAX. (VGS = 2.5 V, ID = 1.0 A)
P-Channel RDS(on)1 = 115 mΩ MAX. (VGS = –4.5 V, ID = –1.5 A)
RDS(on)2 = 120 mΩ MAX. (VGS = –4.0 V, ID = –1.5 A)
RDS(on)3 = 190 mΩ MAX. (VGS = –2.5 V, ID = –1.0 A)
• Low input capacitance
N-Channel Ciss = 160 pF TYP.
P-Channel Ciss = 370 pF TYP.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA1793G
Power SOP8
Gate
PACKAGE DRAWING (Unit: mm)
85
14
5.37 Max.
N-Channel 1 ; Source 1
2 ; Gate 1
7, 8 ; Drain 1
P-Channel 3 ; Source 2
4 ; Gate 2
5, 6 ; Drain 2
6.0 ±0.3
4.4
0.8
1.27 0.78 Max.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
EQUIVALENT CIRCUIT
Drain
Drain
Body
Diode
Gate
Body
Diode
Gate
Protection
Diode
Source
N-Channel
Gate
Protection
Diode
Source
P-Channel
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G16059EJ1V0DS00 (1st edition)
Date Published September 2002 NS CP(K)
Printed in Japan
©
2002
1 page  
µPA1793
TYPICAL CHARACTERISTICS (TA = 25°C)
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A) N-Channel
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
0
0 25 50 75 100 125 150 175
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
100
10
Mounted on ceramic substrate
of 5500 mm2 x 2.2 mm, 1 unit
ID(pulse)
ID(DC)
PW = 100 µs
2.8
2.4
2
1.6
1.2
0.8
0.4
0
0
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
Mounted on ceramic substrate of
5500 mm2 x 2.2 mm
2 units
1 unit
25 50 75 100 125 150 175
TA - Ambient Temperature - °C
1 DC
RDS(on) limited
(at VGS = 4.5 V)
0.1 Power dissipation
limited
0.01
TA = 25°C
Single pulse
0.1
1
10
1 ms
10 ms
100 ms
100
VDS - Drain to Source Voltage - V
1000
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100
Rth(ch-A) = 73.5°C/W
10
1
0.1
Mounted on ceramic substrate of
5500 mm2 x 2.2 mm
Single pulse, 1 unit, TA = 25°C
0.01
100 µ
1m
10 m
100 m
1
PW - Pulse Width - s
10
100 1000
DataSheet G16059EJ1V0DS
5
5 Page 
[MEMO]
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µPA1793
DataSheet G16059EJ1V0DS
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet UPA1793.PDF ] | |
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