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PDF EP9315 Data sheet ( Hoja de datos )
| Número de pieza | EP9315 | |
| Descripción | Enhanced Universal Platform System-on-Chip Processor | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de EP9315 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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EP9315 Data Sheet
FEATURES
• 200-MHz ARM920T Processor
• 16-kbyte Instruction Cache
• 16-kbyte Data Cache
• Linux®, Microsoft® Windows® CE-enabled MMU
• 100-MHz System Bus
• MaverickCrunch™ Math Engine
• Floating Point, Integer, and Signal Processing
Instructions
• Optimized for digital music compression and
decompression algorithms.
• Hardware interlocks allow in-line coding.
• MaverickKey™ IDs
• 32-bit Unique ID can be used for DRM-compliant
128-bit random ID.
• Integrated Peripheral Interfaces
• 32-bit SDRAM Interface (up to 4 Banks)
• 32-/16-bit SRAM / FLASH / ROM
• Serial EEPROM Interface
• EIDE (up to 2 devices)
• 1/10/100-Mbps Ethernet MAC
• Three UARTs
• Three-port USB 2.0 Full-speed Host (OHCI)
(12 Mbits per second)
• LCD and Raster Interface with Graphics
Accelerator
Enhanced Universal Platform
System-on-Chip Processor
• IrDA Interface
• PCMCIA Interface
• Touchscreen Interface with ADC
• 8 x 8 Keypad Scanner
• One Serial Peripheral Interface (SPI™) Port
• 6-channel or 2-channel Serial Audio Interface (I2S)
• 2-channel, Low-cost Serial Audio Interface (AC'97)
• 2 High-resolution PWMs (16 bits each)
• Internal Peripherals
• 12 Direct Memory Access (DMA) Channels
• Real-time Clock with Software Trim
• Dual PLL controls all clock domains.
• Watchdog Timer
• Two General-purpose 16-bit Timers
• One General-purpose 32-bit Timer
• One 40-bit Debug Timer
• Interrupt Controller
• Boot ROM
• Package
• 352-pin PBGA
Serial
Audio
Interface
(3) UARTs
w/
IrDA
(3) USB
Hosts
Ethernet
MAC
Peripheral Bus
Clocks &
Timers
12-channel DMA
MaverickKeyTM
Boot
ROM
MaverickCrunchTM
ARM920T
D-Cache I-Cache
16KB
16KB
MMU
Bus
Bridge
Interrupts
& GPIO
Keypad &
Touch
Screen I/F
Processor Bus
EIDE
I/F
SRAM & Flash I/F
PCMCIA
Unified
SDRAM I/F
Video/LCD
Controller
Graphics
Accelerator
http://www.cirrus.com
MEMORY AND STORAGE
©Copyright 2005 Cirrus Logic (All Rights Reserved)
MAR ‘05
DS638PP4
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List of Tables
EP9315
Enhanced Universal Platform SOC Processor
Table A. Change History .......................................................................................................... 2
Table B. General Purpose Memory Interface Pin Assignments .............................................. 6
Table C. IDE Interface Pin Assignments .................................................................................. 7
Table D. Ethernet Media Access Controller Pin Assignments ................................................. 7
Table E. Audio Interfaces Pin Assignment .............................................................................. 7
Table F. LCD Interface Pin Assignments ................................................................................ 8
Table G. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8
Table H. 64-Key Keypad Interface Pin Assignments ............................................................... 8
Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 9
Table J. Triple Port USB Host Pin Assignments ..................................................................... 9
Table K. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9
Table L. Real-Time Clock with Pin Assignments ................................................................... 10
Table M.PLL and Clocking Pin Assignments ........................................................................ 10
Table N. External Interrupt Pin Assignment ........................................................................... 10
Table O. Dual LED Pin Assignments ..................................................................................... 10
Table P. General Purpose Input/Output Pin Assignment ...................................................... 11
Table Q. Reset and Power Management Pin Assignments ................................................... 11
Table R. Hardware Debug Interface ...................................................................................... 11
Table S. PCMCIA Interface ................................................................................................... 11
Table R. 352 Pin Diagram Dimensions .................................................................................. 56
Table S. Pin Descriptions ..................................................................................................... 60
Table T. Pin Multiplex Usage Information ............................................................................. 62
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©Copyright 2005 Cirrus Logic (All Rights Reserved)
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Table P. General Purpose Input/Output Pin Assignment
Pin Mnemonic
Pin Name - Description
EGPIO[15:0]
FGPIO[7:0]
Expanded General Purpose Input / Output
Pins with Interrupts
Expanded General Purpose Input / Output
Pins with Interrupts
Note: Port F defaults as PCMCIA pins. Port F must be
configured by software to be used as GPIO.
Reset and Power Management
The chip may be reset through the PRSTn pin or through
the open drain common reset pin, RSTOn.
Clocks are managed on a peripheral-by-peripheral basis
and may be turned off to conserve power.
The processor clock is dynamically adjustable from 0 to
200 MHz (184 MHz for industrial conditions).
Table Q. Reset and Power Management Pin Assignments
Pin Mnemonic
Pin Name - Description
PRSTn
RSTOn
Power On Reset
User Reset In/Out – Open Drain –
Preserves Real Time Clock value
Hardware Debug Interface
The JTAG interface allows use of ARM’s Multi-ICE or
other in-circuit emulators.
Note: The JTAG interface does not support boundary scan.
Table R. Hardware Debug Interface
Pin Mnemonic
Pin Name - Description
TCK
TDI
TDO
TMS
TRSTn
JTAG Clock
JTAG Data In
JTAG Data Out
JTAG Test Mode Select
JTAG Port Reset
Internal Boot ROM
The Internal 16-kbyte ROM allows booting from FLASH
memory, SPI or UART. Consult the EP93xx User’s
Manual for operational details
EP9315
Enhanced Universal Platform SOC Processor
12-channel DMA Controller
The DMA module contains 12 separate DMA channels.
Ten of these may be used for peripheral-to-memory or
memory-to-peripheral access. Two of these are
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.
The request bus is a collection of requests, Serial Audio,
and UARTs. Each DMA channel can be used
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can be independently programmed to increment,
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.
PCMCIA Interface
The EP9315 has a single PCMCIA port which can be
used to access either 8 or 16-bit devices.
Table S. PCMCIA Interface
Pin Mnemonic
Pin Name - Description
VS1
VS2
MCD1
MCD2
MCBVD1
MCBVD2
MCDIR
MCDAENn
MCADENn
MCREGn
MCEHn
MCELn
IORDn
IOWRn
MCRDn
MCWRn
READY
WP
MCWAITn
MCRESETn
Voltage sense
Voltage sense
Card detect
Card detect
Voltage detection / status change
Voltage detection
Data transceiver direction control
Data bus transceiver enable
Address bus transceiver enable
Memory card register
Memory card high byte select
Memory card low byte select
I/O card read
I/O card write
Memory card read
Memory card write
Ready / interrupt
Write protect
Wait Input
Card reset
DS638PP4
©Copyright 2005 Cirrus Logic (All Rights Reserved)
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| PDF Descargar | [ Datasheet EP9315.PDF ] | |
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