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PDF EP9312 Data sheet ( Hoja de datos )
| Número de pieza | EP9312 | |
| Descripción | Universal Platform System-on-chip Processor | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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EP9312 Data Sheet
FEATURES
• 200-MHz ARM920T Processor
• 16-kbyte Instruction Cache
• 16-kbyte Data Cache
• Linux®, Microsoft® Windows® CE-enabled MMU
• 100-MHz System Bus
• MaverickCrunch™ Math Engine
• Floating Point, Integer, and Signal Processing
Instructions
• Optimized for digital music compression and
decompression algorithms.
• Hardware interlocks allow in-line coding.
• MaverickKey™ IDs
• 32-bit unique ID can be used for DRM-compliant,
128-bit random ID.
• Integrated Peripheral Interfaces
• 32-bit SDRAM Interface (up to 4 banks)
• 32/16-bit SRAM / FLASH / ROM
• Serial EEPROM Interface
• EIDE (up to 2 devices)
• 1/10/100 Mbps Ethernet MAC
• Three UARTs
• Three-port USB 2.0 Full-speed Host (OHCI)
(12 Mbits per second)
• LCD and Raster Interface
• Touchscreen Interface with ADC
Universal Platform
System-on-chip Processor
• IrDA Interface
• 8 x 8 Keypad Scanner
• One Serial Peripheral Interface (SPI) Port
• 6-channel or 2-channel Serial Audio Interface (I2S)
• 2-channel, Low-cost Serial Audio Interface (AC'97)
• 2 High-resolution PWMs (16 bits each)
• Internal Peripherals
• 12 Direct Memory Access (DMA) Channels
• Real-time Clock with Software Trim
• Dual PLL controls all clock domains.
• Watchdog Timer
• Two General-purpose 16-bit Timers
• One General-purpose 32-bit Timer
• One 40-bit Debug Timer
• Interrupt Controller
• Boot ROM
• Package
• 352 pin PBGA
Serial
Audio
Interface
(3) UARTs
w/
IrDA
(3) USB
Hosts
Ethernet
MAC
Peripheral Bus
12 DCMHAANwN/ EL
DCMRAC
MMaavveerircickkLKocekyTTMM
Boot
ROM
MaverickCrunchTM
ARM920T
D-Cache I-Cache
16KB
16KB
MMU
Clocks &
Timers
Interrupts
& GPIO
Bus
Bridge
Keypad &
Touch
Screen I/F
Processor Bus
EIDE
I/F
SRAM &
Flash I/F
Unified
SDRAM I/F
Video/LCD
Controller
http://www.cirrus.com
MEMORY AND STORAGE
©Copyright 2005 Cirrus Logic (All Rights Reserved)
MAR ‘05
DS515PP7
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List of Tables
EP9312
Universal Platform SOC Processor
Table A. Change History .......................................................................................................... 2
Table B. General Purpose Memory Interface Pin Assignments .............................................. 6
Table C. IDE Interface Pin Assignments .................................................................................. 7
Table D. Ethernet Media Access Controller Pin Assignments ................................................. 7
Table E. Audio Interfaces Pin Assignment .............................................................................. 7
Table F. LCD Interface Pin Assignments ................................................................................ 8
Table G. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8
Table H. 64-Key Keypad Interface Pin Assignments ............................................................... 8
Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 9
Table J. Triple Port USB Host Pin Assignments ..................................................................... 9
Table K. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9
Table L. Real-Time Clock with Pin Assignments ..................................................................... 9
Table M.PLL and Clocking Pin Assignments ........................................................................ 10
Table N. Interrupt Controller Pin Assignment ........................................................................ 10
Table O. Dual LED Pin Assignments ..................................................................................... 10
Table P. General Purpose Input/Output Pin Assignment ...................................................... 10
Table Q. Reset and Power Management Pin Assignments ................................................... 10
Table R. Hardware Debug Interface ...................................................................................... 11
Table R. 352 Pin Diagram Dimensions .................................................................................. 54
Table S. Pin Descriptions ..................................................................................................... 59
Table T. Pin Multiplex Usage Information ............................................................................. 60
DS515PP7
©Copyright 2005 Cirrus Logic (All Rights Reserved)
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Hardware Debug Interface
The JTAG interface allows use of ARM’s Multi-ICE or
other in-circuit emulators.
Table R. Hardware Debug Interface
Pin Mnemonic
Pin Name - Description
TCK
TDI
TDO
TMS
TRSTn
JTAG Clock
JTAG Data In
JTAG Data Out
JTAG Test Mode Select
JTAG Port Reset
EP9312
Universal Platform SOC Processor
12-channel DMA Controller
The DMA module contains 12 separate DMA channels.
Ten of these may be used for peripheral-to-memory or
memory-to-peripheral access. Two of these are
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.
The request bus is a collection of requests, Serial Audio
and UARTs. Each DMA channel can be used
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can be independently programmed to increment,
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.
Internal Boot ROM
The Internal 16 Kbyte ROM allows booting from FLASH
memory, SPI or UART. Consult the EP93xx User’s Guide
for operational details.
DS515PP7
©Copyright 2005 Cirrus Logic (All Rights Reserved)
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EP9312.PDF ] | |
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