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PDF IDTCSPT857C Data sheet ( Hoja de datos )

Número de pieza IDTCSPT857C
Descripción 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDTCSPT857C Hoja de datos, Descripción, Manual

IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
www.DataSheet4U.com
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V - 2.6V PHASE LOCKED
LOOP DIFFERENTIAL 1:10
SDRAM CLOCK DRIVER
IDTCSPT857C
FEATURES:
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
• Operating frequency: 60MHz to 220MHz
• Very low skew:
– <100ps for PC1600 - PC2700
– <75ps for PC3200
• Very low jitter:
– <75ps for PC1600 - PC2700
– <50ps for PC3200
• 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700
• 2.6V AVDD and 2.6V VDDQ for PC3200
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56-
pin VFBGA packages
DESCRIPTION:
The CSPT857C is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK, CLK ) to 10 differential output
pairs (Y[0:9],Y[0:9]) and one differential pair of feedback clock output (FBOUT,
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the input frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption of less than 200µA.
The CSPT857C requires no external components and has been optimised
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycleovertheoperatingvoltageandtemperaturerange.TheCSPT857C,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPT857C is available in Commercial Temperature Range (0°C to
+70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering
Information for details.
APPLICATIONS:
• Meets or exceeds JEDEC standard JESD 82-1A for registered
DDR clock driver
• Meets proposed DDR1-400 specification
• For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),
PC2700 (DDR333), PC3200 (DDR400)
• Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859,
SSTVF16859, DDR1 register, provides complete solution for
DDR1 DIMMs
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2003 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
JUNE 2003
DSC-6201/13

1 page




IDTCSPT857C pdf
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
www.DataSheet4U.com
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
AVDD
Supply Voltage
VDDQ– 0.12
VDDQ I/O Supply Voltage
PC1600-PC2700
2.3
PC3200
2.5
TA OperatingFree-AirTemperature
-40
Typ.
VDDQ
2.5
2.6
Max. Unit
2.7 V
2.7 V
2.7
+85 °C
PIN DESCRIPTION (TSSOP/TVSOP)
Pin Name
Pin Number
AGND
17
AVDD
16
CLK, CLK
13, 14
FBIN, FBIN
35, 36
FBOUT, FBOUT
32, 33
GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48
PWRDWN
37
VDDQ 4, 11, 12, 15, 21, 28, 34, 38, 45
Y[0:9] 3, 5, 10, 20, 22, 27, 29, 39, 44, 46
Y[0:9] 2, 6, 9, 19, 23, 26, 30, 40, 43, 47
Description
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,CLK
PIN DESCRIPTION (VFBGA)
Pin Name
Pin Number
AGND
H1
AVDD
G2
CLK, CLK
F1, F2
FBIN, FBIN
F5, F6
FBOUT, FBOUT
H6, G5
GND A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
PWRDWN
E6
VDDQ B3, B4, E1, E2, E5, G1, G6, J3, J4
Y[0:9] A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
Y[0:9] A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
Description
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,CLK
PIN DESCRIPTION (MLF)
Pin Name
Pin Number
AGND
9
AVDD
8
CLK, CLK
5, 6
FBIN, FBIN
25, 26
FBOUT, FBOUT
21, 22
GND 1, 10
PWRDWN
27
VDDQ 4, 7, 13, 18, 23, 24, 28, 33, 38
Y[0:9] 3, 12, 14, 17, 19, 29, 32, 34, 37, 39
Y[0:9] 2, 11, 15, 16, 20, 30, 31, 35, 36, 40
Description
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,CLK
5

5 Page





IDTCSPT857C arduino
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
www.DataSheet4U.com
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
Yx, FBOUT
Yx, FBOUT
CLK
CLK
FBIN
FBIN
tcycle n
tcycle n+1
tjit(cc) = tcycle n tcycle n+1
Figure 3. Cycle-to-Cycle jitter
t(Ø)n
t(Ø)n + 1
t(Ø) =
n=N
1 t(Ø)n
N
(N is a large number of samples)
Figure 4. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure 5. Output Skew
11

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