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PDF LM25061 Data sheet ( Hoja de datos )

Número de pieza LM25061
Descripción Positive Low Voltage Power Limiting Hot Swap Controller
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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LM25061
July 15, 2009
Positive Low Voltage Power Limiting Hot Swap Controller
General Description
The LM25061 positive hot swap controller provides intelligent
control of the power supply voltage to the load during insertion
and removal of circuit cards from a live system backplane or
other "hot" power sources. The LM25061 provides in-rush
current control to limit system voltage droop and transients.
The current limit and power dissipation in the external series
pass N-Channel MOSFET are programmable, ensuring op-
eration within the Safe Operating Area (SOA). The POWER
GOOD output indicates when the output voltage exceeds a
programmable threshold. The input under-voltage level and
hysteresis are programmable, as well as the initial insertion
delay time and fault detection time. The LM25061-1 latches
off after a fault detection, while the LM25061-2 automatically
restarts at a fixed duty cycle. The LM25061 is available in a
10 pin MSOP package.
Features
Operating range: +2.9V to +17V
In-rush current limit for safe board insertion into live power
sources
Programmable maximum power dissipation in the external
pass device
Adjustable current limit
Circuit breaker function for severe over-current events
Internal high side charge pump and gate driver for external
N-channel MOSFET
Adjustable under-voltage lockout (UVLO) and hysteresis
Adjustable output voltage monitoring and hysteresis
Initial insertion timer allows ringing and transients to
subside after system connection
Programmable fault timer avoids nuisance trips
Active high open drain POWER GOOD output
Available in latched fault and automatic restart versions
Applications
Server Backplane Systems
Base Station Power Distribution Systems
Solid State Circuit Breaker
Package
MSOP-10
Typical Application
Positive Power Supply Control
30090301
© 2009 National Semiconductor Corporation 300903
www.national.com

1 page




LM25061 pdf
Symbol
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Parameter
VCL Threshold voltage
tCL Response time
ISENSE
SENSE input current
Circuit Breaker
VCB
tCB
Threshold voltage
Response time
Timer (TIMER pin)
VTMRH
VTMRL
Upper threshold
Lower threshold
ITIMER
DCFAULT
tFAULT
Insertion time current
Sink current, end of insertion time
Fault detection current
Fault sink current
Fault Restart Duty Cycle
Fault to GATE low delay
FB Pin
FBTH
FBHYS
FBDEL
FB threshold
FB hysteresis current
FB delay
FBBIAS
FB bias current
Power Good (PGD pin)
PGDVOL
PGDIOH
Output low voltage
Off leakage current
Conditions
Min. Typ. Max. Units
VIN-SENSE voltage
45 50 55 mV
VIN-SENSE stepped from 0 mV to
80 mV
15
µs
Enabled, SENSE = OUT
23 µA
Disabled, OUT = 0V
12
Enabled, OUT = 0V
62
VIN - SENSE
VIN - SENSE stepped from 0 mV to
150 mV, time to GATE low, no load
75
95 110
0.19 0.36
mV
µs
Restart cycles (LM25061-2)
End of 8th cycle (LM25061-2)
Re-enable Threshold (LM25061-1)
TIMER pin = 2V
LM25061-2 only
TIMER pin reaches the upper
threshold
1.60
0.9
-7.5
1.5
-110
1.6
1.72
1.0
0.3
0.3
-5.5
2
-80
2.5
0.67
20
1.85
1.1
-3.5
2.5
-50
3.4
V
V
V
V
µA
mA
µA
µA
%
µs
UVLO = 2V
FB = 2V
Delay to PGD high
Delay to PGD low
FB = 1V
1.145
-28
1.17 1.195
-22 -17
100
110
1
V
µA
ns
µA
ISINK = 2 mA
VPGD = 17V
15 30 mV
1 µA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kresistor into each pin.
Note 3: OUT bias current (disabled) due to leakage current through an internal 1.0 Mresistance from SENSE to VOUT.
Note 4: For detailed information on soldering plastic MSOP packages refer to the Packaging Databook available from National Semiconductor Corporation.
Note 5: Current out of a pin is indicated as a negative number.
5 www.national.com

5 Page





LM25061 arduino
control the current delivered to the load. During the in-rush
wwlimw.itDinagtaiSnhteerevta4lU(.tc2oimn Figure 3) an internal 80 µA fault timer
current source charges CT. If Q1’s power dissipation and the
input current reduce below their respective limiting thresholds
before the TIMER pin reaches 1.72V the 80 µA current source
is switched off, and CT is discharged by the internal 2.5 µA
current sink (t3 in Figure 3). The in-rush limiting interval is
complete when the load current reduces to the normal oper-
ating level. The PGD pin switches high when the output
voltage exceeds the threshold programmed at the FB pin.
If the TIMER pin voltage reaches 1.72V before in-rush current
limiting or power limiting ceases (during t2), a fault is declared
and Q1 is turned off. See the Fault Timer & Restart section
for a complete description of the fault mode.
FIGURE 3. Power Up Sequence (Current Limit only)
30090313
Gate Control
A charge pump provides the voltage at the GATE pin to en-
hance the N-Channel MOSFET’s gate. During normal oper-
ating conditions (t3 in Figure 3) the gate of Q1 is held charged
by an internal 20 µA current source. The voltage at the GATE
pin (with respect to ground) is limited by an internal 19.5V
zener diode. See the graph “GATE Pin voltage”. Since the
gate-to-source voltage applied to Q1 could be as high as
19.5V during various conditions, a zener diode with the ap-
propriate voltage rating must be added between the GATE
and OUT pins if the maximum VGS rating of the selected
MOSFET is less than 19.5V. The external zener diode must
have a forward current rating of at least 260 mA.
When the system voltage is initially applied, the GATE pin is
held low by a 260 mA pull-down current. This helps prevent
an inadvertent turn-on of the MOSFET through its drain-gate
capacitance as the applied system voltage increases.
During the insertion time (t1 in Figure 3) the GATE pin is held
low by a 2 mA pull-down current. This maintains Q1 in the off-
state until the end of t1, regardless of the voltage at VIN or
UVLO.
Following the insertion time, during t2 in Figure 3, the gate
voltage of Q1 is modulated to keep the current or power dis-
sipation level from exceeding the programmed levels. While
in the current or power limiting mode the TIMER pin capacitor
is charging. If the current and power limiting cease before the
TIMER pin reaches 1.72V the TIMER pin capacitor then dis-
charges, and the circuit enters normal operation.
If the in-rush limiting condition persists such that the TIMER
pin reached 1.72V during t2, the GATE pin is then pulled low
by the 2 mA pull-down current. The GATE pin is then held low
until either a power up sequence is initiated (LM25061-1), or
until the end of the restart sequence (LM25061-2). See the
Fault Timer & Restart section.
11 www.national.com

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