|
|
PDF DS25BR101 Data sheet ( Hoja de datos )
| Número de pieza | DS25BR101 | |
| Descripción | (DS25BR100 / DS25BR101) 3.125 Gbps LVDS Buffer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS25BR101 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
DS25BR100 / DS25BR101
August 11, 2009
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and
Receive Equalization
General Description
The DS25BR100 and DS25BR101 are single channel 3.125
Gbps LVDS buffers optimized for high-speed signal trans-
mission over lossy FR-4 printed circuit board backplanes and
balanced metallic cables. Fully differential signal paths en-
sure exceptional signal integrity and noise immunity.
The DS25BR100 and DS25BR101 feature transmit pre-em-
phasis (PE) and receive equalization (EQ), making them ideal
for use as a repeater device. Other LVDS devices with similar
IO characteristics include the following products. The
DS25BR120 features four levels of pre-emphasis for use as
an optimized driver device, while the DS25BR110 features
four levels of equalization for use as an optimized receiver
device. The DS25BR150 is a buffer/repeater with the lowest
power consumption and does not feature transmit pre-em-
phasis nor receive equalization.
Wide input common mode range allows the receiver to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires minimal
space on the board while the flow-through pinout allows easy
board layout. On the DS25BR100 the differential input and
output is internally terminated with a 100Ω resistor to lower
return losses, reduce component count and further minimize
board space. For added design flexibility the 100Ω input ter-
minations on the DS25BR101 have been eliminated. This
enables a designer to adjust the termination for custom inter-
connect topologies and layout.
Features
■ DC - 3.125 Gbps low jitter, high noise immunity, low power
operation
■ Receive equalization reduces ISI jitter due to media loss
■ Transmit pre-emphasis drives lossy backplanes and
cables
■ On-chip 100Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space. The DS25BR101 eliminates the
on-chip input termination for added design flexibility.
■ 7 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 3 mm x 3 mm LLP-8 space saving package
Applications
■ Clock and data buffering
■ Metallic cable driving and equalization
■ FR-4 equalization
Typical Application
© 2009 National Semiconductor Corporation 201791
20179110
www.national.com
1 page  
Symbol
Parameter
LwVwDwS.DIaNtPaSUhTeDetC4US.cPoEmCIFICATIONS (IN+, IN-)
VID
VTH
VTL
VCMR
Input Differential Voltage (Note 8)
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
IIN Input Current
CIN Input Capacitance
RIN Input Termination Resistor (Note 9)
SUPPLY CURRENT
ICC Supply Current
Conditions
VCM = +0.05V or VCC-0.05V
VID = 100 mV
VIN = GND or 3.6V
VCC = 3.6V or 0.0V
Any LVDS Input Pin to GND
Between IN+ and IN-
EQ = 0, PE = 0
Min Typ Max Units
0 1V
0 +100 mV
−100 0
mV
0.05
VCC -
0.05
V
±1 ±10 μA
1.7 pF
100 Ω
35 43 mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Input Differential Voltage (VID) The DS25BR100 limits input amplitude to 1 volt. The DS25BR101 supports any VID within the supply voltage to GND
range.
Note 9: Input Termination Resistor (RIN) The DS25BR100 provides an integrated 100 ohm input termination for the high speed LVDS pair. The DS25BR101
eliminates this internal termination.
Note 10: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
5 www.national.com
5 Page 
www.DataSheet4U.com
20179113
Typical LVPECL Driver DC-Coupled Interface to DS25BR100 Input
Note: DS25BR101 requires external 100Ω input termination.
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS25BR101.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS25BR100 | DS25BR100/101 3.125Gbps LVDS Buffer w/Transmit Pre-Empha Rcve Equalization (Rev. F) |  Texas Instruments |
| DS25BR100 | 3.125 Gbps LVDS Buffer | National Semiconductor |
| DS25BR100 | (DS25BR100 / DS25BR101) 3.125 Gbps LVDS Buffer | National Semiconductor |
| DS25BR101 | DS25BR100/101 3.125Gbps LVDS Buffer w/Transmit Pre-Empha Rcve Equalization (Rev. F) | Texas Instruments |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |