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PDF LM25088 Data sheet ( Hoja de datos )
| Número de pieza | LM25088 | |
| Descripción | Wide Input Range Non-Synchronous Buck Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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LM25088
June 5, 2009
Wide Input Range Non-Synchronous Buck Controller
General Description
The LM25088 high voltage non-synchronous buck controller
features all the necessary functions to implement an efficient
high voltage buck converter using a minimum number of ex-
ternal components. The LM25088 can be configured to op-
erate over an ultra-wide input voltage range of 4.5V to 42V.
This easy to use controller includes a level shifted gate driver
capable of controlling an external N-channel buck switch. The
control method is based upon peak current mode control uti-
lizing an emulated current ramp. The use of an emulated
control ramp reduces noise sensitivity of the pulse-width mod-
ulation circuit, allowing reliable control of very small duty
cycles necessary in high input voltage/low output voltage ap-
plications. The LM25088 switching frequency is pro-
grammable from 50 kHz to 1 MHz.
The LM25088 is available in two versions: The LM25088-1
provides a +/-5% frequency dithering function to reduce the
conducted and radiated EMI, while the LM25088-2 provides
a versatile restart timer for overload protection. Additional
features include a low dropout bias regulator, tri-level enable
input to control shutdown and standby modes, soft-start and
oscillator synchronization capability. The device is available
in a thermally enhanced TSSOP-16EP pin package.
Features
■ Emulated current mode control
■ Drives external high-side N-channel MOSFET
■ Ultra-wide input voltage range from 4.5V to 42V
■ Low IQ Shutdown and Standby modes
■ High duty cycle ratio feature for reduced dropout voltage
■ Spread spectrum EMI reduction (LM25088-1)
■ Hiccup timer for overload protection (LM25088-2)
■ Adjustable output voltage from 1.205V with 1.5% feedback
reference accuracy
■ Wide bandwidth error amplifier
■ Single resistor oscillator frequency setting
■ Oscillator synchronization capability
■ Programmable soft-start
■ High voltage, low dropout bias regulator
■ Thermal shutdown protection
Package
■ TSSOP-16EP
Simplified Application Schematic
© 2009 National Semiconductor Corporation 300876
30087601
www.national.com
1 page  
Symbol Parameter
OwSwCwI.LDLaAtaTSOheRe(t4RUT.cPoimn)
Conditions
Min Typ Max Units
LM25088-2 (Non-Dithering)
Fnom1
Fnom2
Nominal Oscillator Frequency
RRT =31.6 kΩ
RRT = 11.3 kΩ
LM25088-1 (Dithering)
180 200 220 kHz
430 500 565 kHz
Fmin
Fmax
SYNC
Dithering Range
Minimum Dither Frequency
Maximum Dither Frequency
Fnom-5%
Fnom+5%
kHz
kHz
SYNC positive threshold
2.3 V
SYNC Pulse Width
15 150 ns
CURRENT LIMIT
VCS(TH)
Cycle by cycle sense voltage threshold VRAMP = 0V
Cycle by Cycle Current Limit Delay
VRAMP = 2.5V
Buck Switch VDS protection
VIN to SW
112 120 136 mV
280 ns
1.5 V
CURRENT LIMIT RESTART (RES Pin)
Vresup
RES Threshold Upper (rising)
Vresdown RES Threshold Lower (falling)
Icharge
Charge source current
Idischarge Discharge sink current
Irampdown Discharge sink current -(post fault)
RAMP GENERATOR
VCS = 0.125
VCS >= 0.125
VCS < 0.125
1.1 1.2 1.3 V
0.1 0.2 0.3 V
40 50 65 µA
20 27 34 µA
0.8 1.2 1.6 µA
IRAMP1
IRAMP2
RAMP Current 1
RAMP Current 2
VOUT Bias Current
RAMP Output Low Voltage
HIGH SIDE (HG) GATE DRIVER
VVIN = 36V, VOUT = 10V
VVIN = 10V, VOUT = 10V
VOUT = 24V
VVIN = 36V, VOUT = 10V
135 165 195 µA
18 25 30 µA
125 µA
200 mV
VOLH
VOHH
IOHH
IOLH
HG Low-state Output Voltage
HG High-state Output Voltage
HG Rise Time
HG Fall Time
Peak HG Source Current
Peak HG Sink Current
BOOT UVLO
IHG = 100 mA
IHG = -100 mA, VOHH = VBOOT - VHG
Cload = 1000 pF
Cload = 1000 pF
VHG = 0V
VHG = VVCC
BOOT to SW
115 215 mV
240 mV
12 ns
6 ns
1.5 A
2A
3V
Pre RDS(ON) Pre-Charge Switch ON- resistance
Pre-Charge switch ON time
IVCC = 1 mA
72 Ω
300 ns
THERMAL
TSD Thermal Shutdown Temperature
Thermal Shutdown Hysterisis
Junction Temperature Rising
Junction Temperature Falling
165 °C
25 °C
θJC Thermal Resistance
θJA Thermal Resistance
Junction to Case
Junction to Ambient
6 °C /W
40 °C /W
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 3: RAMP and COMP are output pins. As such they are not specified to have an external voltage applied.
Note 4: Typical specifications represent the most likely parametric norm at 25°C operation.
Note 5: For detailed information on soldering plastic MSOP packages refer to the Packaging Data Book available from National Semiconductor Corporation.
5 www.national.com
5 Page 
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FIGURE 3. Composition of Current Sense Signal
30087607
The sample & hold DC level illustrated in Figure 3 is derived
from a measurement of the re-circulating (or free-wheeling)
diode current. The diode current flows through the current
sense resistor connected between the CS and CSG pins. The
voltage across the sense resistor is sampled and held just
prior to the onset of the next conduction interval of the buck
switch. The diode current sensing and sample & hold provide
the DC level for the reconstructed current signal. The positive
slope inductor current ramp is emulated by an external ca-
pacitor connected from the RAMP pin to GND and an internal
voltage controlled current source. The ramp current source
that emulates the inductor current is a function of the VIN and
VOUT voltages per the following equation:
IRAMP = 5 µA/V x (VIN x VOUT) + 25 µA
Proper selection of the RAMP capacitor depends upon the
selected value of the output inductor and the current sense
resistor (RS). For proper current emulation, the DC sample &
hold value and the ramp amplitude must have the same de-
pendence on the load current. That is:
Where, gm is the ramp current generator transconductance (5
µA/V) and A is the gain of the current sense amplifier (10V/
V). The RAMP capacitor should connected directly to the
RAMP and GND pins of the IC.
For duty cycles greater than 50%, peak current mode control
circuits are subject to sub-harmonic oscillation. Sub-harmonic
oscillation is normally characterized by alternating wide and
narrow pulses at the SW pin. Adding a fixed slope voltage
ramp (slope compensation) to the current sense signal pre-
vents this oscillation. The 25 µA offset current supplied by the
emulated current source provides a fixed slope to the ramp
signal. In some high output voltage, high duty cycles applica-
tions; additional slope compensation may be required. In
these applications, a pull-up resistor may be added between
the RAMP and VCC pins to increase the ramp slope com-
pensation. A formula to configure pull-up resistor is shown in
Applications Information section.
Dropout Voltage Reduction
The LM25088 features unique circuitry to reduce the dropout
voltage. Dropout voltage is defined as the difference between
the minimum input voltage to maintain regulation and the out-
put voltage (VINmin - Vout). Dropout voltage thus determines
the lowest input voltage at which the converter maintains reg-
ulation. In a buck converter, dropout voltage primarily de-
pends upon the maximum duty cycle. The maximum duty
cycle is dependant on the oscillator frequency and minimum
off-time.
An approximation for the dropout voltage is:
11 www.national.com
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet LM25088.PDF ] | |
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