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PDF MAX1224 Data sheet ( Hoja de datos )
| Número de pieza | MAX1224 | |
| Descripción | (MAX1224 / MAX1225) 12-Bit ADCs | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX1224 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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19-3271; Rev 0; 5/04
www.DataSheet4U.com
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
General Description
The MAX1224/MAX1225 low-power, high-speed, serial-
output, 12-bit, analog-to-digital converters (ADCs) oper-
ate at up to 1.5Msps. These devices feature true-differen-
tial inputs, offering better noise immunity, distortion
improvements, and a wider dynamic range over single-
ended inputs. A standard SPI™/QSPI™/MICROWIRE™
interface provides the clock necessary for conversion.
These devices easily interface with standard digital signal
processor (DSP) synchronous serial interfaces.
The MAX1224/MAX1225 operate from a single +2.7V to
+3.6V supply voltage and require an external reference.
The MAX1224 has a unipolar analog input, while the
MAX1225 has a bipolar analog input. These devices fea-
ture a partial power-down mode and a full power-down
mode for use between conversions, which lower the sup-
ply current to 1mA (typ) and 1µA (max), respectively. Also
featured is a separate power-supply input (VL), which
allows direct interfacing to +1.8V to VDD digital logic. The
fast conversion speed, low-power dissipation, good AC
performance, and DC accuracy (±1.5 LSB INL) make the
MAX1224/MAX1225 ideal for industrial process control,
motor control, and base-station applications.
The MAX1224/MAX1225 come in a 12-pin TQFN pack-
age, and are available in the commercial (0°C to +70°C)
and extended (-40°C to +85°C) temperature ranges.
Data Acquisition
Bill Validation
Motor Control
Applications
Communications
Portable Instruments
Pin Configuration
Features
♦ 1.5Msps Sampling Rate
♦ Only 18mW (typ) Power Dissipation
♦ Only 1µA (max) Shutdown Current
♦ High-Speed, SPI-Compatible, 3-Wire Serial Interface
♦ 69dB S/(N + D) at 525kHz Input Frequency
♦ Internal True-Differential Track/Hold (T/H)
♦ External Reference
♦ No Pipeline Delays
♦ Small 12-Pin TQFN Package
Ordering Information
PART
MAX1224CTC-T
MAX1224ETC-T
MAX1225CTC-T
MAX1225ETC-T
TEMP RANGE
PIN-
PACKAGE
0°C to +70°C 12 TQFN-12
-40°C to +85°C 12 TQFN-12
0°C to +70°C 12 TQFN-12
-40°C to +85°C 12 TQFN-12
INPUT
Unipolar
Unipolar
Bipolar
Bipolar
Typical Operating Circuit
TOP VIEW
AIN+ N.C. SCLK
12 11 10
AIN- 1
REF 2
RGND 3
MAX1224
MAX1225
9 CNVST
8 DOUT
7 VL
456
VDD N.C. GND
TQFN
+2.7V TO +3.6V
+1.8V TO VDD
10µF
DIFFERENTIAL +
INPUT
VOLTAGE -
REF
4.7µF
0.01µF
0.01µF
VDD
0.01µF
VL
AIN+ DOUT
AIN-
MAX1224
MAX1225 CNVST
SCLK
REF
RGND
GND
10µF
µC/DSP
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Typical Operating Characteristics
(VDD = +3V, VL = VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = TMIN to TMAX, unless otherwise noted. Typical val-
ues are measured at TA = +25°C)
MAXIMUM RECOMMENDED fSCLK vs. VL
25
23
21
19
17
1.8 2.1 2.4 2.7 3.0 3.3 3.6
VL (V)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1224)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
0
1024 2048 3072
DIGITAL OUTPUT CODE
4096
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1225)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-2048
-1024
0
1024
DIGITAL OUTPUT CODE
2048
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1224)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
0
1024 2048 3072
DIGITAL OUTPUT CODE
4096
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1225)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-2048
-1024
0
1024
DIGITAL OUTPUT CODE
2048
OFFSET ERROR
vs. TEMPERATURE (MAX1224)
0
-1
-2
-3
-4
-40
-15 10 35 60
TEMPERATURE (°C)
85
OFFSET ERROR
vs. TEMPERATURE (MAX1225)
2
GAIN ERROR
vs. TEMPERATURE (MAX1224)
2
GAIN ERROR
vs. TEMPERATURE (MAX1225)
2
1 11
0 00
-1 -1 -1
-2
-40
-15 10 35 60
TEMPERATURE (°C)
85
-2
-40
-15 10 35 60
TEMPERATURE (°C)
85
-2
-40
-15 10 35 60
TEMPERATURE (°C)
85
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Partial Power-Down and
Full Power-Down Modes
Power consumption can be reduced significantly by plac-
ing the MAX1224/MAX1225 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wake-
up time applications. Pull CNVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 1mA. Drive CNVST
low and allow at least 14 SCLK cycles to elapse before
driving CNVST high to exit partial power-down mode.
Full power-down mode is ideal for infrequent data sam-
pling and very low supply-current applications. The
MAX1224/MAX1225 have to be in partial power-down
mode in order to enter full power-down mode. Perform
the SCLK/CNVST sequence described above to enter
partial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power-
down mode. In partial/full power-down mode, maintain
a logic low or a logic high on SCLK to minimize power
consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1224. Figure 9 shows the bipolar transfer function for
the MAX1225. The MAX1224 output is straight binary,
while the MAX1225 output is two’s complement.
Applications Information
External Reference
An external reference is required for the MAX1224/
MAX1225. Use a 4.7µF and 0.01µF bypass capacitor on
the REF pin for best performance. The reference input
structure allows a voltage range of +1V to VDD.
How to Start a Conversion
An analog-to-digital conversion is initiated by CNVST and
clocked by SCLK, and the resulting data is clocked out
on DOUT by SCLK. With SCLK idling high or low, a falling
edge on CNVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CNVST is low during
the 16th falling SCLK edge, DOUT returns to high imped-
ance on the next rising edge of CNVST or SCLK,
enabling the serial interface to be shared by multiple
devices. If CNVST returns high after the 14th, but before
the 16th SCLK rising edge, DOUT remains active so con-
tinuous conversions can be sustained. The highest
throughput is achieved when performing continuous con-
versions. Figure 10 illustrates a conversion using a typical
serial interface.
CNVST
SCLK
DOUT
MODE
FIRST 8-BIT TRANSFER
EXECUTE PARTIAL POWER-DOWN TWICE
SECOND 8-BIT TRANSFER
1ST SCLK RISING EDGE
1ST SCLK RISING EDGE
0 0 0 D11 D10 D9 D8 D7
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
00000000
NORMAL
PPD RECOVERY FPD
Figure 7. SPI Interface—Full Power-Down Mode
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX1224.PDF ] | |
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