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PDF MAX1279 Data sheet ( Hoja de datos )
| Número de pieza | MAX1279 | |
| Descripción | (MAX1277 / MAX1279) 12-Bit ADCs | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX1279 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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19-3365; Rev 0; 8/04
www.DataSheet4U.com
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
General Description
The MAX1277/MAX1279 are low-power, high-speed, seri-
al-output, 12-bit, analog-to-digital converters (ADCs) with
an internal reference that operates at up to 1.5Msps.
These devices feature true-differential inputs, offering bet-
ter noise immunity, distortion improvements, and a wider
dynamic range over single-ended inputs. A standard
SPI™/QSPI™/MICROWIRE™ interface provides the clock
necessary for conversion. These devices easily interface
with standard digital signal processor (DSP) synchronous
serial interfaces.
The MAX1277/MAX1279 operate from a single +2.7V to
+3.6V supply voltage. The MAX1277/MAX1279 include a
2.048V internal reference. The MAX1277 has a unipolar
analog input, while the MAX1279 has a bipolar analog
input. These devices feature a partial power-down mode
and a full power-down mode for use between conver-
sions, which lower the supply current to 2mA (typ) and
1µA (max), respectively. Also featured is a separate
power-supply input (VL), which allows direct interfacing to
+1.8V to VDD digital logic. The fast conversion speed,
low-power dissipation, excellent AC performance, and DC
accuracy (±1 LSB INL) make the MAX1277/MAX1279
ideal for industrial process control, motor control, and
base-station applications.
The MAX1277/MAX1279 come in a 12-pin TQFN pack-
age, and are available in the commercial (0°C to +70°C)
and extended (-40°C to +85°C) temperature ranges.
Data Acquisition
Bill Validation
Motor Control
Applications
Communications
Portable Instruments
Pin Configuration
TOP VIEW
AIN+ N.C. SCLK
12 11 10
AIN- 1
REF 2
RGND 3
MAX1277
MAX1279
9 CNVST
8 DOUT
7 VL
456
VDD N.C. GND
TQFN
Features
♦ 1.5Msps Sampling Rate
♦ Only 22mW (typ) Power Dissipation
♦ Only 1µA (max) Shutdown Current
♦ High-Speed, SPI-Compatible, 3-Wire Serial Interface
♦ 68.5dB S/(N + D) at 525kHz Input Frequency
♦ Internal True-Differential Track/Hold (T/H)
♦ Internal 2.048V Reference
♦ No Pipeline Delays
♦ Small 12-Pin TQFN Package
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
MAX1277ACTC-T 0°C to +70°C 12 TQFN-12
MAX1277BCTC-T 0°C to +70°C 12 TQFN-12
MAX1277AETC-T -40°C to +85°C 12 TQFN-12
MAX1277BETC-T -40°C to +85°C 12 TQFN-12
MAX1279ACTC-T 0°C to +70°C 12 TQFN-12
MAX1279BCTC-T 0°C to +70°C 12 TQFN-12
MAX1279AETC-T -40°C to +85°C 12 TQFN-12
MAX1279BETC-T -40°C to +85°C 12 TQFN-12
INPUT
Unipolar
Unipolar
Unipolar
Unipolar
Bipolar
Bipolar
Bipolar
Bipolar
Typical Operating Circuit
+2.7V TO +3.6V
+1.8V TO VDD
10µF 0.01µF
0.01µF
VDD VL
DIFFERENTIAL +
INPUT
VOLTAGE -
4.7µF
0.01µF
AIN+ DOUT
AIN-
MAX1277
MAX1279 CNVST
SCLK
REF
RGND
GND
10µF
µC/DSP
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Typical Operating Characteristics
(VDD = +3V, VL = VDD, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured
at TA = +25°C.)
MAXIMUM RECOMMENDED fSCLK vs. VL
25
23
21
19
17
1.8 2.1 2.4 2.7 3.0 3.3 3.6
VL (V)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1277)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
0
1024 2048 3072
DIGITAL OUTPUT CODE
4096
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1279)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-2048
-1024 0 1024
DIGITAL OUTPUT CODE
2048
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1277)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
0
1024 2048 3072
DIGITAL OUTPUT CODE
4096
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (MAX1279)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-2048
-1024 0 1024
DIGITAL OUTPUT CODE
2048
OFFSET ERROR
vs. TEMPERATURE (MAX1277)
0
-1
-2
-3
-4
-5
-6
-40
-15 10 35 60
TEMPERATURE (°C)
85
OFFSET ERROR
vs. TEMPERATURE (MAX1279)
0
GAIN ERROR
vs. TEMPERATURE (MAX1277)
4
GAIN ERROR
vs. TEMPERATURE (MAX1279)
2
-1 3 1
-2 2 0
-3 1 -1
-4 0 -2
-5 -1 -3
-6
-40
-15 10 35 60
TEMPERATURE (°C)
85
-2
-40
-15 10 35 60
TEMPERATURE (°C)
85
-4
-40
-15 10 35 60
TEMPERATURE (°C)
85
_______________________________________________________________________________________ 5
5 Page 
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1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. Figures 1
and 5 show timing diagrams, which outline the serial-
interface operation.
A CNVST falling edge initiates a conversion sequence;
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the conver-
sion is determined.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions tDOUT after each
SCLK’s rising edge and remains valid 4ns (tDHOLD)
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 12 data bits and 3 leading zeros, at least 16
rising clock edges are needed to shift out these bits.
For continuous operation, pull CNVST high between the
14th and the 16th SCLK rising edges. If CNVST stays
low after the falling edge of the 16th SCLK cycle, the
DOUT line goes to a high-impedance state on either
CNVST’s rising edge or the next SCLK’s rising edge.
Partial Power-Down and
Full Power-Down Modes
Power consumption can be reduced significantly by plac-
ing the MAX1277/MAX1279 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wake-
up time applications. Pull CNVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 2mA. While in par-
tial power-down mode, the reference remains enabled to
allow valid conversions once the IC is returned to normal
mode. Drive CNVST low and allow at least 14 SCLK
cycles to elapse before driving CNVST high to exit partial
power-down mode.
Full power-down mode is ideal for infrequent data sam-
pling and very low supply current applications. The
MAX1277/MAX1279 have to be in partial power-down
mode to enter full power-down mode. Perform the
SCLK/CNVST sequence described above to enter par-
tial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power-
down mode. While in full power-down mode, the refer-
ence is disabled to minimize power consumption. Be
sure to allow at least 2ms recovery time after exiting full
power-down mode for the reference to settle. In
partial/full power-down mode, maintain a logic low or a
logic high on SCLK to minimize power consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1277. Figure 9 shows the bipolar transfer function for
the MAX1279. The MAX1277 output is straight binary,
while the MAX1279 output is two’s complement.
Applications Information
Internal Reference
The MAX1277/MAX1279 have an on-chip voltage refer-
ence trimmed to 2.048V. The internal reference output
is connected to REF and also drives the internal capac-
itive DAC. The output can be used as a reference volt-
age source for other components and can source up to
2mA. Bypass REF with a 0.01µF capacitor and a 4.7µF
capacitor to RGND.
The internal reference is continuously powered up dur-
ing both normal and partial power-down modes. In full
power-down mode, the internal reference is disabled.
Be sure to allow at least 2ms recovery time after hard-
ware power-up or exiting full power-down mode for the
reference to reach its intended value.
CNVST
SCLK
DOUT
FIRST 8-BIT TRANSFER
EXECUTE PARTIAL POWER-DOWN TWICE
SECOND 8-BIT TRANSFER
1ST SCLK RISING EDGE
1ST SCLK RISING EDGE
0 0 0 D11 D10 D9 D8 D7
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
00000000
MODE
NORMAL
PPD RECOVERY
FPD
REF
ENABLED (2.048V)
DISABLED
Figure 7. SPI Interface—Full Power-Down Mode
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MAX1279.PDF ] | |
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