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PDF CH7303 Data sheet ( Hoja de datos )

Número de pieza CH7303
Descripción Chrontel CH7303 HDTV / DVI Encoder
Fabricantes Chrontel 
Logotipo Chrontel Logotipo



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No Preview Available ! CH7303 Hoja de datos, Descripción, Manual

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CH7303
Preliminary Advanced Information
Chrontel CH7303 HDTV / DVI Encoder
Features
General Description
• Digital Visual Interface (DVI) Transmitter up to 165M The CH7303 is a Display Controller device which accepts a
pixels/second
• DVI low jitter PLL
• DVI hot plug detection
• Analog YPrPb outputs for HDTV
• HDTV support for 480p, 576p, 720p, 1080i and 1080p
• MacrovisionTM copy protection support for HDTV
digital graphics input signal, and encodes and transmits data
through a DVI link (DFP can also be supported), VGA ports
(analog RGB) or a HDTV port (YPrPb). The device is able to
encode the video signals and generate synchronization signals
for analog HDTV interface standards and graphics standards
up to UXGA. The device accepts data over one 15-bit wide
variable voltage data port which supports 9 different data
• Programmable digital input interface supporting RGB formats including RGB and YCrCb.
(15, 16, 24 or 30 bit) and YCrCb input data formats
• Can output either RGB or YPrPb
• TV / Monitor connection detect
• Programmable power management
• Three 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
The DVI processor includes a low jitter PLL for
generation of the high frequency serialized clock, and all
circuitry required to encode, serialize and transmit data.
The CH7303 is able to drive a DFP display at a pixel rate
of up to 165MHz, supporting UXGA resolution displays.
No scaling of input data is performed on the data output
to the DVI device.
• Offered in a 64-pin LQFP package
• Backward pin compatible with CH7301 or CH7009/11
• Support three additional 15 bit multiplexed RGB Input
In addition to DVI encoder modes, bypass modes are included
which perform color space conversion to HDTV standards
and generate and insert HDTV sync signals, or output VGA
Data Format (IDF 6,7.8)
style analog RGB for use as a CRT DAC.
† Patent number 5,781,241
¥ Patent number 5,914,753
Note: Other names and brands may be claimed as property by others.
HPDET
GPIO[1:0]
AS
SPC
SPD
RESET*
H,V
DE
VREF
2
XCLK,XCLK* 2
D[14:0] 15
ISET
Serial
Port
Control
H,V,DE
Latch
/
2
/
24
Clock
Driver
Data
Latch, /
Demux 30
Color Space
/ Conversion
24 Sync Decode
/
30
DVI Encode
DVI PLL
DVI
Serialize
DVI Driver
/ TLC, TLC*
2
/ TDC0, TDC0*
2
/
TDC1, TDC1*
2
/
TDC2, TDC2*
2
/
HSYNC,
2 VSYNC
HDTV
YPbPr
RGB
MUX
DAC 2
DAC 1
DAC 0
Three
10-bit DAC's
DAC[2]
DAC[1]
DAC[0]
Figure 1: Functional Block Diagram
209-0000-031 Rev. 0.4, 8/26/2002
1

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CH7303 pdf
CHRONTELwww.DataSheet4U.com
2.0 Functional Description
CH7303
2.1 TV Output Operation
The CH7303 is capable of being operated as in one of several bypass modes for driving monitors requiring component
video signals (HDTV, multi-sync monitors, etc.). All modes make use of the same set of DAC’s, and therefore cannot
be used simultaneously. Table 2 describes the possible operating modes. A ‘p’ following a number in the Input Scan
Type column indicates a progressive scan (non-interlaced) input where the number indicates the active number of lines
per frame. An ‘i’ following a number in the Input Scan Type column indicates an interlaced input where the number
indicates the active number of lines per frame. Detailed descriptions of each of the operating modes follows Table 2.
Table 2: Operating Modes
Input Scan
Input Data
Type
Format
non-interlaced RGB
non-interlaced
(480p, 576p,
720p)
Interlaced
(1080i)
non-interlaced
(1080p)
RGB /
YCrCb1
RGB /
YCrCb1
RGB /
YCrCb1
Output scan
Type
non-interlaced
non-interlaced
interlaced
non-interlaced
Output
Format
RGB
YpbPr2,3
YpbPr3
YpbPr3
Operating Mode
RGB bypass
HDTV/EDTV bypass
HDTV/EDTV bypass
(1080i)
HDTV/EDTV bypass
(1080p)
2.1.1
HDTV / EDTV Bypass
In HDTV / EDTV Bypass mode, data, sync and clock signals are input to the CH7303 from a graphics device in the
scanning method that matches the display device (interlaced data is sent to the CH7303 to drive an interlaced display,
non-interlaced data is sent to the CH7303 to drive a non-interlaced display). The input data format can be YCrCb or
RGB. Horizontal and vertical sync signals must either be sent to the CH7303 from the graphics device or embedded in
the data stream according to SMPTE standards. Data is 2X multiplexed, and the XCLK clock signal can be 1X or 2X
times the pixel rate. Input data is color space converted to the selected video format, has sync signals generated and is
output from the video DAC’s. The output format is YPbPr. The graphics resolutions supported for HDTV Bypass mode
are shown in Table 3 below. The resolutions supported for EDTV Bypass mode are shown in Table 3 below.
Table 3: HDTV Bypass
Active
Resolution
Total
Resolution
1280x720
1650x750
1280x720
1920x1080
1648x750
2200x1125
1920x1080
1920x1080
1920x1080
2640x1125
2376x1250
2200x1125
1920x1080
1920x1080
1920x1080
1920x1080
2640x1125
2750x1125
2752x1125
2376x1250
Scan Type
Non-Interlaced
Non-Interlaced
Interlaced
Interlaced
Interlaced
Non-Interlaced
Non-Interlaced
Non-Interlaced
Non-Interlaced
Non-Interlaced
Pixel Clock
(MHz)
74.25
74.25/1.001
74.160
74.25
74.25/1.001
74.25
74.25
148.5
148.5/1.001
74.25
74.25/1.001
148.5
74.25
74.25
74.25/1.001
74.304
148.5
Frame Rate
(Hz)
60
60/1.001
60
30
30/1.001
25
25
60
60/1.001
30
30/1.001
50
25
24
24/1.001
24
50
Standard
SMPTE 296M
SMPTE 274M
SMPTE 274M
SMPTE 295M
SMPTE 274M
SMPTE 274M
SMPTE 274M
SMPTE 295M
209-0000-031 Rev. 0.4, 8/26/2002
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CH7303 arduino
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3.3 Electrical Characteristics
(Operating Conditions: TA = 0°C – 70°C, VDD =3.3V ± 5%)
Symbol
IVDD
IVDDV
IPD
Description
Video D/A Resolution
Full scale output current
Video level error
Total supply current
VDDV (1.8V) current (15pF load)
Total Power Down Current
CH7303
Min
10
Typ
10
33.9
TBD
4
0.06
Max
10
10
Units
bits
mA
%
mA
mA
mA
3.4 DC Specifications
Symbol
Description
Test Condition Min Typ Max Unit
VSDOL
SPD (serial port data) Output
Low Voltage
IOL = 2.0 mA
0.4 V
VSPIH
Serial Port (SPC, SPD) Input
High Voltage
1.0
VDD + 0.5
V
VSPIL
Serial Port (SPC, SPD) Input
Low Voltage
GND-0.5
0.4 V
VHYS
VDATAIH
VDATAIL
VMISCIH
Hysteresis of Inputs
D[0-14] Input High Voltage
D[0-14] Input Low Voltage
GPIOx, RESET*, AS, HPDET
Input High Voltage
DVDD=3.3V
0.25
Vref+0.25
GND-0.5
2.7
DVDD+0.5
Vref-0.25
VDD + 0.5
V
V
V
V
VMISCIL
GPIOx, RESET*, AS, HPDET DVDD=3.3V
Input Low Voltage
GND-0.5
0.6 V
IMISCPU
Pull Up Current
(GPIO, RESET*, AS)
VIN = 0V
0.5
5.0 uA
IMISCPD
Pull Down Current
(HPDET)
VIN = 3.3V
0.5
5.0 uA
VMISCOH
GPIOx, VSYNC, HSYNC
Output High Voltage
IOH = -0.4mA
DVDD-0.2
V
VMISCOL
GPIOx, VSYNC, HSYNC
Output Low Voltage
IOL = 3.2mA
0.2 V
VH
DVI Single Ended Output
TVDD = 3.3V ± 5%
TVDD –
High Voltage
RTERM = 50Ω ± 1%
0.01
VL
DVI Single Ended Output Low RSWING = 2400Ω ± 1%
TVDD –
Voltage
0.6
TVDD +
0.01
TVDD –
0.4
V
V
VSWING
DVI Single Ended Output
Swing Voltage
400 600 mVp-p
VOFF
DVI Single Ended Standby
Output Voltage
TVDD –
0.01
TVDD +
0.01
V
209-0000-031 Rev. 0.4, 8/26/2002
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