|
|
PDF ICS581-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS581-01 | |
| Descripción | (ICS581-01/-02) Zero-Delay Glitch-Free Clock Multiplexer | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS581-01 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
ICS581-01, -02
Zero-Delay Glitch-Free Clock Multiplexer
Description
Features
The ICS581-01 and ICS581-02 are glitch free,
Phase Locked Loop (PLL) based clock multiplexers
(mux) with zero delay from input to output. They
each have 4 low skew outputs which can be
configured as a single output, 3 outputs or 4
outputs. The ICS581-01 allows user control over
the mux switching. The ICS581-02 has automatic
switching between the 2 clock inputs.
The ICS581-01 and -02 are members of the ICS
Clock Blocks™ family of clock generation,
synchronization, and distribution devices. For a
non-PLL based clock mux, see the ICS580-01.
Block Diagrams
• Tiny 16 pin TSSOP package
• No short pulses or glitches on output. Operates to
200 MHz
• User controlled (ICS581-01) or automatic, timed
(ICS581-02) switch
• Low skew outputs
• Ideal for systems with backup or redundant clocks
• Zero delay, input to output
• 50% output duty cycle allows duty cycle correction
• Spread Smart™ technology works with spread
spectrum parts
INA
INB
FBIN
ICS581-01
1
0
SELA
OE0
OE1
CLK1
OE0
CLK2
PLL
2 CLK3
S0, S1
CLK4
OE1
External Feedback
÷48 1
÷3 0
IN NO_INA
Transition
Detector
DIV
INA 1
INB 0
CLK1
OE0
CLK2
FBIN
ICS581-02
PLL
OE0 2
OE1 S0, S1
CLK3
CLK4
External Feedback
OE1
MDS 581-01, 581-02 A
1 Revision 041100
Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
1 page  
www.DataSheet4U.com
ICS581-01, -02
Zero-Delay Glitch-Free Clock Multiplexer
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS
Minimum Typical Maximum Units
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
Ambient Operating Temperature
ICS581G-01I
Soldering Temperature
Max of 10 seconds
Storage temperature
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH
INA and INB only
Input Low Voltage, VIL
INA and INB only
Input High Voltage, VIH
Non-clock inputs
Input Low Voltage, VIL
Non-clock inputs
Output High Voltage, VOH
IOH=-12mA
Output Low Voltage, VOL
IOL=12mA
Operating Supply Current, IDD
100 MHz inputs, no Load
Short Circuit Current
On-chip pull-up resistor
Input Capacitance
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
-0.5
0
-40
-65
3.0
(VDD/2)+1
2
VDD-0.5
VDD/2
VDD/2
26
±70
250
4
7
VDD+0.5
70
85
260
150
5.5
(VDD/2)-1
0.8
0.5
V
V
°C
°C
°C
°C
V
V
V
V
V
V
V
mA
mA
kΩ
pF
Input Frequency
Note 6
6
200 MHz
Input Clock Duty Cycle
at VDD/2
30
70 %
Skew, selected input clock to FBIN
Note 1
-250 0
250 ps
Skew, between any output clocks
Note 2
-250 0
250 ps
Transition Detector Timeout, DIV=0
ICS581-02 only
2 3 4 INB periods
Transition Detector Timeout, DIV=1
ICS581-02 only
32 48 64 INB periods
Frequency Transition Time, 50 to 150 MHz Note 3, 4
70 200 µs
Frequency Transition Time, 100 to 100 MHz Note 3, 5
4 10 µs
Output Clock Rise Time
0.8 V to 2 V
1 2 ns
Output Clock Fall Time
2 V to 0.8 V
1 2 ns
Output Clock Duty Cycle, less than 133 MHz at VDD/2, no load
45
55 %
Output Clock Duty Cycle, greater than 133 MHz at VDD/2, no load
40
60 %
Output Clock Duty Cycle with S0=S1=1
at VDD/2, no load
40
60 %
Absolute Output Clock Period Jitter
Deviation from mean
±150
ps
One Sigma Output Clock Period Jitter
40 ps
Note 1. Assumes clocks with same rise times, measured at VDD/2.
Note 2. Assumes identically loaded outputs with identical rise times, measured at VDD/2.
The maximum skew between any 2 clocks is 250 ps not 500 ps.
Note 3. Time taken for output to lock to new clock when mux selection changed from INA to INB.
Note 4 With 50 MHz on INA and 150 MHz on INB.
Note 5. With 100 MHz on both INA and INB, 180° out of phase.
Note 6. For correct operation, FBIN requires a rail to rail clock. At high frequencies, this may mean that the ICS581 output driving
FBIN cannot drive other loads.
MDS 581-01, 581-02 A
5 Revision 041100
Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet ICS581-01.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS581-01 | (ICS581-01/-02) Zero-Delay Glitch-Free Clock Multiplexer | Integrated Circuit Systems |
| ICS581-02 | (ICS581-01/-02) Zero-Delay Glitch-Free Clock Multiplexer | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |