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PDF ICS5314I-01 Data sheet ( Hoja de datos )

Número de pieza ICS5314I-01
Descripción DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
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www.DataSheet4U.com Integrated
Circuit
Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85314I-01 is a low skew, high perfor- 5 differential 2.5V/3.3V LVPECL outputs
ICS
HiPerClockS™
mance 1-to-5 Differential-to-2.5V/3.3V LVPECL
Fanout Buffer and a member of the HiPerClockS™
Selectable differential CLK0, nCLK0 or LVCMOS inputs
family of High Performance Clock Solutions from CLK0, nCLK0 pair can accept the following differential
ICS. The ICS85314I-01 has two selectable clock input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
inputs. The CLK0, nCLK0 pair can accept most standard
differential input levels. The single-ended CLK1 can accept
LVCMOS or LVTTL input levels. The clock enable is internally
synchronized to eliminate runt clock pulses on the outputs
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 700MHz
during asynchronous assertion/deassertion of the clock Translates any single-ended input signal to 3.3V
enable pin.
LVPECL levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS85314I-01 ideal for those applications demand-
ing well defined performance and repeatability.
Output skew: 30ps (maximum), TSSOP package
50ps (maximum), SOIC package
Part-to-part skew: 350ps (maximum)
Propagation delay: 1.8ns (maximum)
RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
LVPECL mode operating voltage supply range:
V = 2.375V to 3.8V, V = 0V
CC EE
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
nCLK_EN
CLK0
nCLK0
CLK1
CLK_SEL
00
11
D
Q
LE
PIN ASSIGNMENT
Q0 1
20 VCC
nQ0 2
19 nCLK_EN
Q1 3
18 VCC
nQ1 4
17 nc
Q0
Q2 5
16 CLK1
nQ0
nQ2 6
15 CLK0
Q1
nQ1
Q3 7
nQ3 8
Q4 9
14 nCLK0
13 nc
12 CLK_SEL
Q2 nQ4 10 11 VEE
nQ2
ICS85314I-01
Q3 20-Lead TSSOP
nQ3 6.5mm x 4.4mm x 0.92mm Package Body
Q4 G Package
nQ4 Top View
ICS85314I-01
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
85314BGI-01
www.icst.com/products/hiperclocks.html
1
REV. E SEPTEMBER 23, 2005

1 page




ICS5314I-01 pdf
www.DataSheet4U.com Integrated
Circuit
Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
VCC - 1.4
VCC - 2.0
0.6
Maximum
VCC - 0.9
VCC - 1.7
1.0
Units
V
V
V
TABLE
5.
AC
CHARACTERISTICS,
V
CC
=
2.375V
TO
3.8V,
V
EE
=
0V,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f
MAX
tjit (Ø)
tpLH
tsk(o)
Output Frequency
CLK0, nCLK0
CLK1
RMS Phase Jitter (Random); NOTE 5
Propagation Delay, Low to High; NOTE 1
Output Skew;
NOTE 3, 6
TSSOP Package
SOIC Package
Integration Range:
(12kHz - 20MHz)
700 MHz
300 MHz
0.05 ps
1.0 1.4 1.8 ns
30 ps
50 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 6
350 ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
CLK0, nCLK0
CLK1
20% to 80%
ƒ700MHz
ƒ250MHz
200
45
45
All parameters measured at fMAX unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Measured from VCC/2 input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: Please refer to the Phase Noise Plot.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
700
55
55
ps
%
%
85314BGI-01
www.icst.com/products/hiperclocks.html
5
REV. E SEPTEMBER 23, 2005

5 Page





ICS5314I-01 arduino
www.DataSheet4U.com Integrated
Circuit
Systems, Inc.
ICS85314I-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT
Zo = 50Ω
FIN
Zo = 50Ω
50Ω
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50Ω
VCC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Zo = 50Ω
FIN
Zo = 50Ω
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
85314BGI-01
www.icst.com/products/hiperclocks.html
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