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PDF ADV3003 Data sheet ( Hoja de datos )

Número de pieza ADV3003
Descripción HDMI/DVI TMDS Equalizer
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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FEATURES
One input, one output HDMI/DVI high speed signal
equalizer/driver
Enables HDMI 1.3 receive-compliant input
Four TMDS channels per input/output
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Fully buffered unidirectional inputs/outputs
Equalized inputs for operation with long HDMI cables
(20 meters at 2.25 Gbps)
Pre-emphasized outputs
Matched 50 Ω input and output on-chip terminations
Low added jitter
Transmitter disable feature
Reduces power dissipation
Disables input terminations
Single-supply operation (3.3 V)
Standards compliant: HDMI receiver, DVI
40-lead, 6 mm × 6 mm, RoHS-compliant LFCSP
APPLICATIONS
Multiple input displays
Advanced television set (HDTV) front panel connectors
HDMI/DVI cable extenders
GENERAL DESCRIPTION
The ADV3003 is a 4-channel transition minimized differential
signaling (TMDS) buffer featuring equalized inputs and
pre-emphasized outputs. The ADV3003 features 50 Ω input
and output terminations, providing full-swing output signal
recovery and minimizing reflections for improved system
signal integrity. The ADV3003 is targeted at HDMI™/DVI
applications and is ideal for use in systems with long cable
runs, long PCB traces, and designs with interior cabling.
The ADV3003 is provided in a 40-lead, LFCSP, surface-mount,
RoHS-compliant, plastic package and is specified to operate
over the −40°C to +85°C temperature range.
HDMI/DVI TMDS Equalizer
ADV3003
FUNCTIONAL BLOCK DIAGRAM
PE_EN TX_EN
VTTI
PARALLEL
CONTROL
CONTROL
LOGIC
ADV3003
AVCC
AVEE
VTTO
IP[3:0]
IN[3:0]
+
44
4 EQ BUFFER PE 4
HIGH SPEED BUFFERED
+ OP[3:0]
ON[3:0]
Figure 1.
TYPICAL APPLICATION DIAGRAM
MEDIA CENTER
SET-TOP BOX
DVD PLAYER
HDMI
RECEIVER
4:1 HDMI
SWITCH
HDTV SET
ADV3003
GAME
CONSOLE
BACK PANEL
CONNECTORS
FRONT PANEL
CONNECTOR
Figure 2.
PRODUCT HIGHLIGHTS
1. Supports data rates up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats and greater than UXGA
(1600 × 1200) DVI resolutions.
2. The 12 dB input cable equalizer enables the use of long
cables at the input. For a typical 24 AWG cable, the
ADV3003 compensates for more than 20 meters at data
rates up to 2.25 Gbps.
3. The selectable 6 dB of output pre-emphasis allows the
ADV3003 to drive high loss output cables or long PCB traces.
4. Matched 50 Ω on-chip input and output terminations
improve system signal integrity.
5. An external control pin, PE_EN, sets the output
pre-emphasis to either 0 dB or 6 dB.
6. An external control pin, TX_EN, simultaneously disables
both the transmitter and the on-chip input terminations.
This feature reduces the power dissipation of the ADV3003
and indicates to a connected source when the ADV3003 is
disabled.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV3003
IN0 1
IP0 2
IN1 3
IP1 4
VTTI 5
IN2 6
IP2 7
IN3 8
IP3 9
AVCC 10
PIN 1
INDICATOR
ADV3003
TOP VIEW
(Not to Scale)
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
23 AVCC
22 AVCC
21 NC
NOTES
1. NC = NO CONNECT.
2. THE ADV3003 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE
OF THE PACKAGE, WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE TO MEET
ELECTRICAL AND THERMAL SPECIFICATIONS.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10, 16, 22, 23, 25, 26, 30, 32
11
12
13
14
15
17
18
19
20
24, 27, 37, ePAD
28
29
21, 31, 33, 34, 35, 36, 38, 39, 40
Mnemonic
IN0
IP0
IN1
IP1
VTTI
IN2
IP2
IN3
IP3
AVCC
ON0
OP0
VTTO
ON1
OP1
ON2
OP2
ON3
OP3
AVEE
TX_EN
PE_EN
NC
Type 1
HS, I
HS, I
HS, I
HS, I
Power
HS, I
HS, I
HS, I
HS, I
Power
HS, O
HS, O
Power
HS, O
HS, O
HS, O
HS, O
HS, O
HS, O
Power
Control
Control
NC
Description
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Positive Analog Supply. 3.3 V nominal.
High Speed Output Complement.
High Speed Output.
Output Termination Supply. Nominally connected to AVCC.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Negative Analog Supply. 0 V nominal.
High Speed Output Enable Parallel Interface.
High Speed Pre-Emphasis Enable Parallel Interface.
No Connect.
1 HS = high speed, I = input, O = output.
Rev. 0 | Page 5 of 16

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The ADV3003 has an external control pin, TX_EN. The
TX_EN pin must be connected to either a logic high (1) or
low (0), in accordance with the logic values set forth in Table 1.
The use of the TX_EN pin is described in Table 5. When the
transmitter is enabled by setting TX_EN to 1, both the input
and output terminations are enabled. Setting TX_EN to 0
disables the transmitter, reducing power when the transmitter
is not in use. When the transmitter is disabled, the input termi-
nation resistors are also disabled to present a high impedance
state at the input and indicate to any connected HDMI sources
that the link through the ADV3003 is inactive.
Table 5. Transmitter Enable Setting
Input
TX_EN Termination
Transmitter
State
0 Off
Off
1 On
On
Output
Termination
On
On
ADV3003
The ADV3003 also includes two levels of programmable output
pre-emphasis, 0 dB and 6 dB. The output pre-emphasis level can
be manually configured by setting the PE_EN pin. The PE_EN
pin must be connected to either a logic high (1) or low (0), in
accordance with the logic values set forth in Table 1. The use of
the PE_EN pin is described in Table 6. No specific cable length
is suggested for use with either pre-emphasis setting, because
cable performance varies widely among manufacturers.
Table 6. Pre-Emphasis Enable Setting
PE_EN
Boost
0 0 dB
1 6 dB
In a typical application, the output of the ADV3003 is
connected to the input of an HDMI/DVI receiver, which
provides a second set of matched terminations in accordance
with the HDMI 1.3 specification. If neither receiver nor receiver
termination is connected to the output of the ADV3003 in the
end-application, each ADV3003 output pin should be tied to 3.3
V through a 50 Ω resistor.
Rev. 0 | Page 11 of 16

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