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PDF ISL12057 Data sheet ( Hoja de datos )

Número de pieza ISL12057
Descripción Low Cost and Low Power I2C RTC Real Time Clock/Calendar
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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ISL12057
® Low Cost and Low Power I2C RTC Real Time Clock/Calendar
Data Sheet
June 15, 2009
FN6755.0
Low Power and Low Cost RTC with Alarm
Function and Dual IRQ pins
The ISL12057 device is a low power real time clock that is
pin compatible and functionally equivalent to Maxim DS1337
with clock/calendar and alarm function.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Pinouts
ISL12057
(8 LD SOIC, MSOP)
TOP VIEW
X1 1
X2 2
IRQ2 3
GND 4
8 VDD
7 IRQ1/FOUT
6 SCL
5 SDA
ISL12057
(8 LD µTDFN)
TOP VIEW
X1 1
X2 2
IRQ2 3
GND 4
8 VDD
7 IRQ1/FOUT
6 SCL
5 SDA
Features
• Pin Compatible to Maxim DS1337
• Functionally Equivalent to Maxim DS1337
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Date, Month, and Year
• Dual Interrupts for Frequency Output and Alarm interrupts
• 4 Selectable Frequency Outputs
• 2 Alarms
- Settable to the Second, Minute, Hour, Day of the Week,
and Date
• I2C Interface
- 400kHz Data Transfer Rate
• Small Package Options
- 8 Ld 2mmx2mm µTDFN
- 8 Ld MSOP
- 8 Ld SOIC
- Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set-Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• Point Of Sale Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL12057 pdf
ISL12057
www.SDaetraiSahleIent4teUr.cfoamce Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP MAX
(Note 5) (Note 6) UNITS NOTES
tBUF
Time the Bus Must Be Free
Before the Start of a New
Transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition
1300
ns
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STO
tDH
tR
tF
Cb
Clock LOW Time
Measured at the 30% of VDD crossing
Clock HIGH Time
Measured at the 70% of VDD crossing
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD
START Condition Hold Time
From SDA falling edge crossing 30% of
VDD to SCL falling edge crossing 70%
of VDD
Input Data Setup Time
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD
Input Data Hold Time
From SCL falling edge crossing 30% of
VDD to SDA entering the 30% to 70%
of VDD window
STOP Condition Setup Time
From SCL rising edge crossing 70% of
VDD, to SDA rising edge crossing 30%
of VDD
STOP Condition Hold Time
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD
Output Data Hold Time
From SCL falling edge crossing 30% of
VDD, until SDA enters the 30% to 70%
of VDD window
SDA and SCL Rise Time
From 30% to 70% of VDD
SDA and SCL Fall Time
From 70% to 30% of VDD
Capacitive Loading of SDA or SCL Total on-chip and off-chip
1300
600
600
600
100
0
600
600
0
20 + 0.1 x Cb
20 + 0.1 x Cb
10
ns
ns
ns
ns
ns
900 ns
ns
ns
ns
300 ns 7, 8
300 ns 7, 8, 9
400 pF 7, 8
Rpu SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about
2kΩ to~2.5kΩ.
For Cb = 40pF, max is about 15kΩ to
~20kΩ
1
kΩ 7, 8
NOTES:
4. IRQ1/FOUT inactive.
5. Typical values are for T = +25°C and 3.3V supply voltage.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits should be considered typical and are not production tested.
8. These are I2C specific parameters and are not production tested, however, they are used to set conditions for testing devices to validate
specification.
9. Parts will work with SDA pull-up voltage above the VPULLUP limit but the tAA and tFin the I2C parameters are not guaranteed.
10. Specified at +25°C.
5 FN6755.0
June 15, 2009

5 Page





ISL12057 arduino
ISL12057
www.DatTaASBhLeEet46U. .AcLomARM1 INTERRUPT WITH ENABLE BITS
SELECTION (Continued)
A1DW/DT A1M1 A1M2 A1M3 A1M4 ALARM1 INTERRUPT
X 1101
Match Hour
0 1110
Match Date
1 1110
Match Day
0 0 0 1 1 Match Second and Minute
0 0 1 0 1 Match Second and Hour
0 0 0 0 0 Match Second, Minute
and Hour
. ....
. ....
.
.
0 1 0 0 0 Match Minute Hour and
Date
0 0 0 0 0 Match Second, Minute
Hour and Date
. ....
. ....
.
.
1 1 0 0 0 Match Minute, Hour, and
Day
1 0 0 0 0 Match Second, Minute,
Hour, and Day
Note: X is don’t care, it can be set to 0 or 1.
Following is example of Alarm1 Interrupt.
Example – A single alarm will occur on Monday at 11:30am
(Monday is when DW = 2).
A. Set Alarm1 registers as follows:
ALARM1
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
A1SC 1 0 0 0 0 0 0 0 80h Seconds disabled
A1MN 0 0 1 1 0 0 0 0 30h Minutes set to 30,
enabled
A1HR
0 1 0 1 0 0 0 1 51h Hours set to 11am,
enabled
A1DW/DT 0 1 0 0 0 0 1 0 42h Day set to 1,
enabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the A1F bit in the
status register to “1”.
Alarm2 Registers
Addresses [Address 12h to 14h]
The Alarm2 register bytes are set up identical to the RTC
register bytes except that the MSB of each byte functions as
an enable bit (enable = “0”). These enable bits specify which
alarm registers (minutes, hour, and date/day) are used to
make the comparison. When all the enable bits are set to “1”,
the Alarm2 will trigger once per minute. Note that there are
no alarm bytes for second, month and year.
The Alarm2 function works as a comparison between the
Alarm2 registers and the RTC registers. As the RTC
advances, the Alarm2 will be triggered once a match occurs
between the Alarm2 registers and the RTC registers. Any
one Alarm2 register, multiple registers, or all registers can be
enabled for a match.
To clear an Alarm2, the A2F status bit must be set to “0” with
a write.
TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS
SELECTION
A2DW/DT A2M2 A2M3 A2M4 ALARM2 INTERRUPT
X 1 1 1 Every Minute (Second=00)
X 011
Match Minute
X 101
Match Hour
0 110
Match Date
1 110
Match Day
X 0 0 1 Match Minute and Hour
0
100
Match Hour and Date
0 0 1 0 Match Minute and Date
0 0 0 0 Match Minute, Hour, and Date
1 0 1 0 Match Minute and Day
1 1 0 0 Match Hour and Day
1 0 0 0 Match Minute, Hour, and Day
Note: X is don’t care, it can be set to 0 or 1.
Following is example of Alarm2 Interrupt.
Example – A single alarm will occur on every 1st day of the
month at 20:00 military time.
A. Set Alarm registers as follows:
ALARM2
BIT
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
A2MN 1 0 0 0 0 0 0 0 80h Minutes disabled
A2HR 0 0 1 0 0 0 0 0 20h Hours set to 20,
enabled
A2DW/DT 0 0 0 0 0 0 0 1 01h Date set to 1st,
enabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 20:00 on Monday (after minutes
changes from 59 to 00) by setting the A2F bit in the status
register to “1”.
11 FN6755.0
June 15, 2009

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