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PDF MAX1181 Data sheet ( Hoja de datos )
| Número de pieza | MAX1181 | |
| Descripción | Low-Power ADC | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-2093; Rev 1; 2/07
www.DataSheetE4VUAA.cLVoUAmAILTAIOBNLEKIT
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
General Description
The MAX1181 is a 3V, dual 10-bit, analog-to-digital
converter (ADC) featuring fully-differential wideband
track-and-hold (T/H) inputs, driving two pipelined, nine-
stage ADCs. The MAX1181 is optimized for low-power,
high-dynamic performance applications in imaging,
instrumentation, and digital communication applica-
tions. The MAX1181 operates from a single 2.7V to 3.6V
supply, consuming only 246mW, while delivering a typi-
cal signal-to-noise ratio (SNR) of 59dB at an input fre-
quency of 20MHz and a sampling rate of 80Msps. The
T/H driven input stages incorporate 400MHz (-3dB)
input amplifiers. The converters may also be operated
with single-ended inputs. In addition to low operating
power, the MAX1181 features a 2.8mA sleep mode, as
well as a 1µA power-down mode to conserve power
during idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of the internal or external
reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1181 features parallel, CMOS-compatible
three-state outputs. The digital output format is set to
two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of 1.7V to 3.6V for flexible interfac-
ing. The MAX1181 is available in a 7mm ✕ 7mm, 48-pin
TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible higher and lower speed versions of the
MAX1181 are also available. Please refer to the
MAX1180 datasheet for 105Msps, the MAX1182
datasheet for 65Msps, the MAX1183 datasheet for
40Msps, and the MAX1184 datasheet for 20Msps. In
addition to these speed grades, this family includes a
20Msps multiplexed output version (MAX1185), for
which digital data is presented time-interleaved on a
single, parallel 10-bit output port.
Applications
High-Resolution Imaging
I/Q Channel Digitization
Multichannel IF Undersampling
Instrumentation
Video Application
Functional Diagram appears at end of data sheet.
Features
♦ Single 3V Operation
♦ Excellent Dynamic Performance
59dB SNR at fIN = 20MHz
73dB SFDR at fIN = 20MHz
♦ Low Power
82mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
♦ 0.02dB Gain and 0.25° Phase Matching (typ)
♦ Wide ±1VP-P Differential Analog Input Voltage
Range
♦ 400MHz, -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ User-Selectable Output Format—Two’s
Complement or Offset Binary
♦ 48-Pin TQFP Package with Exposed Pad for
Improved Thermal Dissipation
♦ Evaluation Kit Available
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1181ECM
-40°C to +85°C
48 TQFP-EP*
MAX1181ECM+
-40°C to +85°C
48 TQFP-EP*
*EP = Exposed paddle.
+Denotes a lead-free package.
Pin Configuration
COM 1
VDD 2
GND 3
INA+ 4
INA- 5
VDD 6
GND 7
INB- 8
INB+ 9
GND 10
VDD 11
CLK 12
MAX1181
EP*
36 D1A
35 D0A
34 OGND
33 OVDD
32 OVDD
31 OGND
30 D0B
29 D1B
28 D2B
27 D3B
26 D4B
25 D5B
48 TQFP-EP
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED
BY A "+" SIGN.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 83.333MHz, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Power Supply Rejection
PSRR
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
CLK Pulse-Width High
CLK Pulse-Width Low
tDO
tENABLE
tDISABLE
tCH
tCL
Wake-Up Time (Note 6)
tWAKE
CHANNEL-TO-CHANNEL MATCHING
Offset
Gain
CONDITIONS
Figure 3 (Note 5)
Figure 4
Figure 4
Figure 3 clock period: 12ns
Figure 3 clock period: 12ns
Wakeup from sleep mode
Wakeup from shutdown
MIN TYP MAX UNITS
±0.2 mV/V
±0.1 %/V
58
10
1.5
6 ±1
6 ±1
0.28
1.5
ns
ns
ns
ns
ns
µs
Crosstalk
Gain Matching
Phase Matching
fINA or B = 20MHz at -0.5dBFS
fINA or B = 20MHz at -0.5dBFS
fINA or B = 20MHz at -0.5dBFS
-70 dB
0.02 ±0.2 dB
0.25 degrees
Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS, referenced to a +1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Typical Operating Characteristics
(VDD = 3V, OVDD = 2.5V, internal reference, differential input at -0.5dBFS, fCLK = 80.0006MHz, CL ≈ 10pF. TA = +25°C, unless other-
wise noted.)
FFT PLOT CHA (8192-POINT RECORD,
DIFFERENTIAL INPUT)
0
-10 CHA
-20
-30
fINA = 6.0449MHz
fINB = 7.5099MHz
fCLK = 80.0006MHz
AINA = -0.46dBFS
FFT PLOT CHB (8192-POINT RECORD,
DIFFERENTIAL INPUT)
0
-10 CHB
-20
-30
fINA = 6.0449MHz
fINB = 7.5099MHz
fCLK = 80.0006MHz
AINB = -0.52dBFS
FFT PLOT CHA (8192-POINT RECORD,
DIFFERENTIAL INPUT)
0
-10 CHA
-20
-30
fINA = 19.9123MHz
fINB = 24.9123MHz
fCLK = 80.0006MHz
AINA = -0.52dBFS
-40 -40 -40
-50 -50 -50
-60 -60 -60
-70 -70 -70
-80 -80 -80
-90 -90 -90
-100
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
-100
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
-100
0
5 10 15 20 25 30 35 40
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________ 5
5 Page 
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Dual 10-Bit, 80Msps, 3V, Low-Power ADC
with Internal Reference and Parallel Outputs
VIN T/H Σ x2 VOUT
VIN T/H Σ x2 VOUT
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
FLASH
ADC
DAC
1.5 BITS
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
DIGITAL CORRECTION LOGIC
T/H 10
DIGITAL CORRECTION LOGIC
T/H 10
VINA D9A–D0A
VINB D9B–D0B
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)
Figure 1. Pipelined Architecture––Stage Blocks
For stability and noise filtering purposes, bypass REFIN
with a > 10nF capacitor to GND. In internal reference
mode, REFOUT, COM, REFP, and REFN become low-
impedance outputs.
In the buffered external reference mode, adjust the ref-
erence voltage levels externally by applying a stable
and accurate voltage at REFIN. In this mode, COM,
REFP, and REFN become outputs. REFOUT may be left
open or connected to REFIN through a > 10kΩ resistor.
In the unbuffered external reference mode, connect
REFIN to GND. This deactivates the on-chip reference
buffers for REFP, COM, and REFN. With their buffers
shut down, these nodes become high impedance and
may be driven through separate external reference
sources.
Clock Input (CLK)
The MAX1181’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
SNR = 20 ✕ log10 (1 / [2π x fIN ✕ tAJ]),
where fIN represents the analog input frequency and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1181 clock input operates with a voltage thresh-
old set to VDD / 2. Clock inputs with a duty cycle other
than 50% must meet the specifications for high and low
periods as stated in the Electrical Characteristics table.
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1181
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 4 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (OE)
All digital outputs, D0A–D9A (Channel A) and D0B–D9B
(Channel B), are TTL/CMOS logic-compatible. There is a
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX1181.PDF ] | |
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