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PDF TC55V400AFT-70 Data sheet ( Hoja de datos )

Número de pieza TC55V400AFT-70
Descripción 16-BIT FULL CMOS STATIC RAM
Fabricantes Toshiba Semiconductor 
Logotipo Toshiba Semiconductor Logotipo



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No Preview Available ! TC55V400AFT-70 Hoja de datos, Descripción, Manual

TC55V400AFT-55,-70
www.DataSheet4U.com TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55V400AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16
bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6
V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5 mA standby
current (at VDD = 3 V, Ta = 25°C, maximum) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low.
There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and
output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte
access. This device is well suited to various microprocessor system applications where high speed, low power and
battery backup are required. And, with a guaranteed operating extreme temperature range of -40° to 85°C, the
TC55V400AFT can be used in environments exhibiting extreme temperature conditions. The TC55V400AFT is
available in normal and reverse pinout plastic 48-pin thin-small-outline package (TSOP).
FEATURES
· Low-power dissipation
Operating: 10.8 mW/MHz (typical)
· Single power supply voltage of 2.3 to 3.6 V
· Power down features using CE1 and CE2
· Data retention supply voltage of 1.5 to 3.6 V
· Direct TTL compatibility for all inputs and outputs
· Wide operating temperature range of -40° to 85°C
· Standby Current (maximum):
3.6 V
3.0 V
7 mA
5 mA
· Access Times (maximum):
TC55V400AFT
-55 -70
Access Time
55 ns
70 ns
CE1 Access Time
55 ns
70 ns
CE2 Access Time
55 ns
70 ns
OE Access Time
30 ns
35 ns
· Package:
TSOP48-P-1214-0.50 (AFT) (Weight: 0.38 g typ)
PIN ASSIGNMENT (TOP VIEW)
48 PIN TSOP
1 48
24 25
(Normal)
PIN NAMES
A0~A17
CE1 , CE2
R/W
OE
LB , UB
I/O1~I/O16
VDD
GND
NC
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A15 A14 A13 A12 A11 A10 A9 A8 NC NC R/W CE2 NC UB LB NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A17 A7 A6 A5 A4 A3 A2 A1 A0 CE1 GND OE I/O1 I/O9 I/O2 I/O10
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
I/O3 I/O11 I/O4 I/O12 VDD I/O5 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8 I/O16 GND NC A16
2001-09-04 1/11

1 page




TC55V400AFT-70 pdf
TC55V400AFT-55,-70
www.DaAtaCSheCetH4UA.cRomACTERISTICS AND OPERATING CONDITIONS
(Ta = -40° to 85°C, VDD = 2.3 to 3.6 V)
READ CYCLE
SYMBOL
PARAMETER
tRC
tACC
tCO1
tCO2
tOE
tBA
tCOE
tOEE
tBE
tOD
tODO
tBD
tOH
Read Cycle Time
Address Access Time
Chip Enable( CE1 ) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
TC55V400AFT
-55 -70
MIN MAX MIN MAX
70 ¾ 85 ¾
¾ 70 ¾ 85
¾ 70 ¾ 85
¾ 70 ¾ 85
¾ 35 ¾ 45
¾ 35 ¾ 45
5¾5¾
0¾0¾
0¾0¾
¾ 30 ¾ 35
¾ 30 ¾ 35
¾ 30 ¾ 35
10 ¾ 10 ¾
UNIT
ns
WRITE CYCLE
SYMBOL
PARAMETER
tWC
tWP
tCW
tBW
tAS
tWR
tODW
tOEW
tDS
tDH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
TC55V400AFT
-55 -70
MIN MAX MIN MAX
70 ¾ 85 ¾
50 ¾ 55 ¾
60 ¾ 70 ¾
50 ¾ 55 ¾
0¾0¾
0¾0¾
¾ 30 ¾ 35
0¾0¾
30 ¾ 35 ¾
0¾0¾
UNIT
ns
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
tR, tF
TEST CONDITION
30 pF + 1 TTL Gate
VDD - 0.2 V, 0.2 V
VDD ´ 0.5
VDD ´ 0.5
5 ns
2001-09-04 5/11

5 Page





TC55V400AFT-70 arduino
www.DataSheet4U.com
TC55V400AFT-55,-70
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
2001-09-04 11/11

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