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PDF TC55V4000ST-70 Data sheet ( Hoja de datos )
| Número de pieza | TC55V4000ST-70 | |
| Descripción | 8-BIT STATIC RAM | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TC55V4000ST-70,-85
www.DataSheet4U.com TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55V4000ST is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits.
Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V
power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 0.5 µA standby
current (at VDD = 3 V, Ta = 25°C) when chip enable ( CE ) is asserted high. There are two control inputs. CE is
used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This
device is well suited to various microprocessor system applications where high speed, low power and battery
backup are required. The TC55V4000ST is available in a normal pinout plastic 32-pin thin-small-outline package
(TSOP).
FEATURES
• Low-power dissipation
Operating: 10.8 mW/MHz (typical)
• Single power supply voltage of 2.3 to 3.6 V
• Power down features using CE
• Data retention supply voltage of 1.5 to 3.6 V
• Direct TTL compatibility for all inputs and outputs
• Standby Current (maximum):
3.6 V
3.0 V
7 µA
5 µA
• Access Times (maximum):
TC55V4000ST
-70 -85
Access Time
70 ns
85 ns
CE Access Time
70 ns
85 ns
OE Access Time
35 ns
45 ns
• Package:
TSOP 32-P-0.50 (ST)
(Weight: 0.24 g typ)
PIN ASSIGNMENT (TOP VIEW)
32 PIN TSOP
16 1
17 32
(Normal pinout)
PIN NAMES
A0~A18
R/W
OE
CE
I/O1~I/O8
VDD
GND
Address Inputs
Read/Write Control
Output Enable
Chip Enable
Data Inputs/Outputs
Power
Ground
Pin No.
Pin Name
Pin No.
Pin Name
12
A11 A9
17 18
A3 A2
3 4 5 6 7 8 9 10 11 12 13 14 15 16
A8 A13 R/W A17 A15 VDD A18 A16 A14 A12 A7 A6 A5 A4
19 20 21 22 23 24 25 26 27 28 29 30 31 42
A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE A10 OE
2001-11-30 1/10
1 page  
TC55V4000ST-70,-85
www.DaAtaCSheCetH4UA.cRomACTERISTICS AND OPERATING CONDITIONS
(Ta = −40° to 85°C, VDD = 2.3 to 3.6 V)
READ CYCLE
SYMBOL
PARAMETER
tRC
tACC
tCO
tOE
tCOE
tOEE
tOD
tODO
tOH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
TC55V4000ST
-70 -85
MIN MAX MIN MAX
85 100
85 100
85 100
45 50
55
00
35 40
35 40
10 10
UNIT
ns
WRITE CYCLE
SYMBOL
PARAMETER
tWC
tWP
tCW
tAS
tWR
tODW
tOEW
tDS
tDH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
TC55V4000ST
-70 -85
MIN MAX MIN MAX
85 100
55 60
70 80
00
00
35 40
00
40 40
00
UNIT
ns
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
tR, tF
TEST CONDITION
30 pF + 1 TTL Gate
VDD − 0.2 V, 0.2 V
VDD × 0.5
VDD × 0.5
5 ns
2001-11-30 5/10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TC55V4000ST-70.PDF ] | |
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