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PDF SC9820P Data sheet ( Hoja de datos )
| Número de pieza | SC9820P | |
| Descripción | MP3 Decoder | |
| Fabricantes | Silan | |
| Logotipo |  |
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SC9820P
MP3 DECODER WITH CD INTERFACE
DESCRIPTION
SC9820P is a sing-chip Mp3 decoder. It can be used in CD
player, DISC-MAN and such systems which need MP3 decoder.
And this chip provides smaller package, lower power dissipation
and higher cost performance ratio.
FEATURES
* Provide ECC and EDC functions for CD-ROM data error
correcting.
* ISO/IEC 11172-3 L3 L2 L1 decode
* ISO/IEC 13818-3 L3 L2 L! decode
* Support all MP3 bit rates and free formats under SO/IEC
11172-3 L3 L2 L1 specifications.
* Support all MP3 bit rates and free formats under SO/IEC
13818-3 L3 L2 L1 specifications.
* Support 48K/44.1K/32K MP3 standard sampling rate,
24K/22.05K/16K and 12K/11.025/8K low sampling rate
* Support single/double/stereo/union stereo
* Serial host interface
* Support CD-DA straight through mode
* Support SDRAM/DRAM interface
* Only one external 16.9344MHz crystal oscillator
* Power supply managing: normal mode, brownout mode and
dormancy mode
* Various playing functions: skip forward/backward in track, skip
forward/backward between tracks, pause, play and so on.
* Support the file systems in ISO9660, Joliet UDF formats
* Support 1M/4M/8M/16Mx16 SDRAM, 1M/4M x16 DRAM
LQPF-64-10x10-0.5
ORDERING INFORMATION
Device
SC9820P
Package
LQFP-64-10X10-0.5
APPLICATIONS
* Desk-top audio
* Portable CD/Mp3 player
* Car audio
HANGZHOU MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.3 2006.06.02
Page 1 of 23
1 page  
www.DataSheet4U.com
SC9820P
(Continued)
Pin No.
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin name
DacWs
DacBck
DacSd
DacSysClk
Ws
Bck
Sd
VDD3.3
XALTI
XALTO
NotExtAsyncReset
TestMode
VSS
VDD1.8
SsiSClk
Data
DataAvail
NC
TestConfig0
TestConfig1
InterruptToMcu
Addr<0>
Addr<1>
Addr<2>
Addr<3>
I/O Pin description
O Word selection clock pin output to DAC.
O Bit clock pin output to DAC.
O Data pin output to DAC.
O System clock output to DAC.
I Word selection clock pin output to CD-DSP.
I Bit clock pin output to CD-DSP.
I Data pin output to CD-DSP.
I Port supply voltage (3.3V).
I Oscillator input pin.
O Oscillator output pin.
I System reset pin which is a low active.
Test mode pin which is a high active and connected to ground
I
when it is not in test mode.
I Ground
I Kernel supply voltage (1.8V)
I MCU clock input pin.
I/O MCU data pin.
I MCU telecommunication control pin.
-- Null
I Test mode configuration ( low level when normal use)
I Test mode configuration ( low level when normal use)
O Interrupt pin which is a high active and output to MCU.
O SDRAM/DRAM address pin 0
O SDRAM/DRAM address pin 1
O SDRAM/DRAM address pin 2
O SDRAM/DRAM address pin 3
FUNCTION DESCRIPTION
1. Register function
Register description (The register address of SC9820P is 8 bits)
Symbol
Address Read/write Initialization
SC9820P play state registers
Description
TotalTimeMin[5:0]
0x61
TotalTimeSec[5:0]
CurrentTimeMin[5:0]
CurrentTimeSec[5:0]
0x62
0x63
0x64
R
R
R
R
0x00
0x00
0x00
0x00
Total time’s minutes of current playing
music:0-59
Total time’s seconds of current playing
music:0-59
Played time’s minutes of current music:0-59
Played time’s seconds of current music: 0-59
(To be continued)
HANGZHOU MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.3 2006.06.02
Page 5 of 23
5 Page 
www.DataSheet4U.com
SC9820P
(Continued)
Symbol
Address Read/write Initialization
Description
bit1:
1: Input is IIS interface
BitStreamType[5:0]
0x76
W
0x00
0: Output is EIAJ interface
bit0:
0: Output word clock has 16 bitclk
1: Output word clock has 24 bitclk
Bit[0]:
CdRomType
0x77
W
0x00
1: CD-ROM XA format disk
Read external RAM registers
0:Common CD-ROM format disk
MemAddrHigh[7:0]
0x7A
W
0x00
High 8 bits of start address when external
RAM outburst method to read
MemAddrMid[7:0]
0x7B
W
0x00
Middle 8 bits of start address when external
RAM outburst method to read
MemAddrLow[7:0]
0x7C
W
0x00
Low 8 bits of start address when external
RAM outburst method to read
External RAM read-write command register
MemCmd[7:0]
0x7D
W
0x01
Bit[7:0]:
0x00: External RAM read command
0x80: External RAM write command
Note: 1. When it is in free mode, do not display the bit rate of current music in FrameInform register. At this time,
the display time is wrong.
2. ForwardSkipFrame is when occurs error, if CD-DSP can not ensure the position of M.S.F needed by
SC9820P, Host denotes SC9820P to skip the number of Second and Frame. Hereinto, the number of
second is stored in InpRegHigh(8’h71), and the number of Frame is stored in InpRegLow(8’h72).
3. The interface data of DAC and word clock are changing at the falling edge of the bit clock.
2. Exchange with the Host
The general purpose register provides parameter for main control conmmand, and output register together with
state register provide some parameters:
1) StartConfigure
InpRegHigh&InpRegLow is a 16 bits unsigned number, if the blank data CdItf input to the buffer is larger
than this threshold, it will startup the next download operation; through configuring this value, the Mp3
debounce time and CD pick up head jump frequency can remain balance; the value has an effective range
related with SDRAM configuration; If the input value exceeds the enable range, the default value will replace
the input value; Before send StartConfigure, the main controller will configure the HramType BitStreamType
and CdRomType.
2) SetUpCDFS
InpRegHigh, InpRegLow, InpReg2High are file start MSF physics address respectively; During file
HANGZHOU MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.3 2006.06.02
Page 11 of 23
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